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comparison python/ppci/target/thumb/arm.brg @ 342:86b02c98a717 devel

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Moved target directory
author Windel Bouwman
date Sat, 01 Mar 2014 15:40:31 +0100
parents python/target/arm.brg@4d204f6f7d4e
children 818be710e13d
comparison
equal deleted inserted replaced
341:4d204f6f7d4e 342:86b02c98a717
1
2 from ppci.target.thumb.instructions import Orr, Lsl, Str2, Ldr2, Ldr3
3 from ppci.target.thumb.instructions import B, Bl, Bgt, Blt, Beq, Bne
4 from ppci.target.thumb.instructions import Mov2, Mov3, Sub3
5 from ppci.target.thumb.instructions import Add3, Sub, Cmp, Sub2, Add2, Mul
6
7 %%
8
9 %terminal ADDI32 SUBI32 MULI32
10 %terminal ORI32 SHLI32
11 %terminal CONSTI32 MEMI32 REGI32 CALL
12 %terminal MOVI32
13
14 %%
15
16
17 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add3, dst=[d], src=[$1, $2]); return d .)
18 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub3, dst=[d], src=[$1, $2]); return d .)
19 reg: ORI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Orr, dst=[], src=[d, $2]); return d .)
20 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Lsl, dst=[], src=[d, $2]); return d .)
21 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Mul, dst=[d], src=[$2, d]); return d .)
22
23 reg: CONSTI32 3 (. d = self.newTmp(); ln = self.selector.frame.addConstant($$.value); self.emit(Ldr3, dst=[d], others=[ln]); return d .)
24 reg: MEMI32(reg) 4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1], others=[0]); return d .)
25 reg: REGI32 1 (. return $$.value .)
26 reg: CALL 1 (. return self.selector.munchCall($$.value) .)
27
28
29 stmt: MOVI32(MEMI32(addr), reg) 3 (. self.emit(Str2, src=[$1, $2]) .)
30
31 addr: reg 2 (. .)