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comparison python/cortexm3.py @ 224:5af52987f5bd

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Fixup of pc rel operand
author Windel Bouwman
date Tue, 09 Jul 2013 17:59:15 +0200
parents 85c8105318e7
children 1c7364bd74c7
comparison
equal deleted inserted replaced
223:85c8105318e7 224:5af52987f5bd
66 r = getRegNum(n) 66 r = getRegNum(n)
67 assert r 67 assert r
68 regs.append(r) 68 regs.append(r)
69 return regs 69 return regs
70 70
71 class MemoryOp: 71 def isRegOffset(regname, x, y):
72 def __init__(self, basereg, offset): 72 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
73 assert type(basereg) is ArmReg 73 return y.number
74 self.basereg = basereg 74 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
75 return x.number
76
77
78 class MemRegXRel:
79 def __init__(self, offset):
80 assert offset % 4 == 0
75 self.offset = offset 81 self.offset = offset
76 82
77 def __repr__(self): 83 def __repr__(self):
78 return '[{}, #{}]'.format(self.basereg, self.offset) 84 return '[{}, #{}]'.format(self.regname, self.offset)
79 85
80 @classmethod 86 @classmethod
81 def Create(cls, vop): 87 def Create(cls, vop):
82 if type(vop) is AUnop and vop.operation == '[]': 88 if type(vop) is AUnop and vop.operation == '[]':
83 vop = vop.arg # descent 89 vop = vop.arg # descent
84 if type(vop) is ABinop: 90 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
85 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber: 91 if type(offset) is int:
86 offset = vop.arg2.number 92 if offset % 4 == 0:
87 basereg = RegOp.Create(vop.arg1)
88 if not basereg:
89 return
90 else:
91 return
92 elif type(vop) is ASymbol:
93 offset = 0
94 basereg = RegOp.Create(vop)
95 if not basereg:
96 return
97 else:
98 return
99 return cls(getRegNum(basereg.num), offset)
100
101 class MemSpRel:
102 def __init__(self, offset):
103 assert offset % 4 == 0
104 self.offset = offset
105
106 def __repr__(self):
107 return '[sp, #{}]'.format(self.offset)
108
109 @classmethod
110 def Create(cls, vop):
111 if type(vop) is AUnop and vop.operation == '[]':
112 vop = vop.arg # descent
113 if type(vop) is ABinop and vop.op == '+':
114 if type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber and vop.arg1.name.upper() == 'SP' and vop.arg2.number % 4 == 0:
115 offset = vop.arg2.number 93 offset = vop.arg2.number
116 return cls(offset) 94 return cls(offset)
117 elif type(vop) is ASymbol and vop.name.upper() == 'SP': 95 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
118 return cls(0) 96 return cls(0)
97
98 class MemSpRel(MemRegXRel):
99 regname = 'SP'
100
101 class MemPcRel(MemRegXRel):
102 regname = 'PC'
119 103
120 class MemoryOpReg8Imm5: 104 class MemoryOpReg8Imm5:
121 def __init__(self, basereg, offset): 105 def __init__(self, basereg, offset):
122 assert type(basereg) is ArmReg 106 assert type(basereg) is ArmReg
123 self.basereg = basereg 107 self.basereg = basereg
257 class loadimm5_ins(LS_imm5_base): 241 class loadimm5_ins(LS_imm5_base):
258 mnemonic = 'LDR' 242 mnemonic = 'LDR'
259 opcode = 0xD 243 opcode = 0xD
260 244
261 class ls_sp_base_imm8(ArmInstruction): 245 class ls_sp_base_imm8(ArmInstruction):
262 operands = (Reg8Op, MemoryOp) 246 operands = (Reg8Op, MemSpRel)
263 def __init__(self, rt, memop): 247 def __init__(self, rt, memop):
264 self.rt = rt 248 self.rt = rt
265 assert memop.basereg.num == 13
266 self.offset = memop.offset 249 self.offset = memop.offset
267 250
268 def encode(self): 251 def encode(self):
269 rt = self.rt.num 252 rt = self.rt.num
270 assert rt < 8 253 assert rt < 8
271 imm8 = self.offset >> 2 254 imm8 = self.offset >> 2
255 print(imm8)
272 assert imm8 < 256 256 assert imm8 < 256
273 h = (self.opcode << 8) | (rt << 8) | imm8 257 h = (self.opcode << 8) | (rt << 8) | imm8
274 return u16(h) 258 return u16(h)
275 259
276 def __repr__(self): 260 def __repr__(self):
278 262
279 @armtarget.instruction 263 @armtarget.instruction
280 class ldr_pcrel(ArmInstruction): 264 class ldr_pcrel(ArmInstruction):
281 """ ldr Rt, [PC, imm8], store value into memory """ 265 """ ldr Rt, [PC, imm8], store value into memory """
282 mnemonic = 'ldr' 266 mnemonic = 'ldr'
283 operands = (RegOp, MemoryOp) 267 operands = (RegOp, MemPcRel)
284 def __init__(self, rt, label): 268 def __init__(self, rt, label):
285 self.rt = rt 269 self.rt = rt
286 self.label = label 270 self.label = label
287 self.offset = 0 271 self.offset = 0
288 272