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comparison python/ppci/target/arm/instructions.py @ 354:5477e499b039

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Added some sort of string functionality
author Windel Bouwman
date Thu, 13 Mar 2014 18:59:06 +0100
parents b8ad45b3a573
children 52492b304adf
comparison
equal deleted inserted replaced
353:b8ad45b3a573 354:5477e499b039
171 171
172 def Mul(*args): 172 def Mul(*args):
173 return Mul1(args[0], args[1], args[2]) 173 return Mul1(args[0], args[1], args[2])
174 174
175 175
176 class Mul(ArmInstruction): 176 class Mul1(ArmInstruction):
177 def __init__(self, rd, rn, rm): 177 def __init__(self, rd, rn, rm):
178 super().__init__() 178 super().__init__()
179 self.rd = rd 179 self.rd = rd
180 self.rn = rn 180 self.rn = rn
181 self.rm = rm 181 self.rm = rm
209 self.token[21:28] = self.opcode 209 self.token[21:28] = self.opcode
210 self.token.cond = 0xE # Always! 210 self.token.cond = 0xE # Always!
211 return self.token.encode() 211 return self.token.encode()
212 212
213 def __repr__(self): 213 def __repr__(self):
214 return 'add {}, {}, {}'.format(self.rd, self.rn, self.rm) 214 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
215 215
216 216
217 class Add1(OpRegRegReg): 217 class Add1(OpRegRegReg):
218 mnemonic = 'ADD'
218 opcode = 0b0000100 219 opcode = 0b0000100
219 220
220 221
221 class Sub1(OpRegRegReg): 222 class Sub1(OpRegRegReg):
223 mnemonic = 'SUB'
222 opcode = 0b0000010 224 opcode = 0b0000010
223 225
224 226
225 class Orr1(OpRegRegReg): 227 class Orr1(OpRegRegReg):
228 mnemonic = 'ORR'
226 opcode = 0b0001100 229 opcode = 0b0001100
227 230
228 231
229 class OpRegRegImm(ArmInstruction): 232 class OpRegRegImm(ArmInstruction):
230 """ add rd, rn, imm12 """ 233 """ add rd, rn, imm12 """
243 self.token[21:28] = self.opcode 246 self.token[21:28] = self.opcode
244 self.token.cond = 0xE # Always! 247 self.token.cond = 0xE # Always!
245 return self.token.encode() 248 return self.token.encode()
246 249
247 def __repr__(self): 250 def __repr__(self):
248 return 'add {}, {}, {}'.format(self.rd, self.rn, self.imm) 251 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm)
249 252
250 253
251 class Add2(OpRegRegImm): 254 class Add2(OpRegRegImm):
255 mnemonic = 'ADD'
252 opcode = 0b0010100 256 opcode = 0b0010100
253 257
254 258
255 class Sub2(OpRegRegImm): 259 class Sub2(OpRegRegImm):
260 mnemonic = 'SUB'
256 opcode = 0b0010010 261 opcode = 0b0010010
257 262
258 263
259 264
260 # Branches: 265 # Branches:
391 396
392 def __repr__(self): 397 def __repr__(self):
393 return '{} {}, [{}, {}]'.format(self.mnemonic, self.rt, self.rn, 398 return '{} {}, [{}, {}]'.format(self.mnemonic, self.rt, self.rn,
394 hex(self.offset)) 399 hex(self.offset))
395 400
401
396 class Str1(LdrStrBase): 402 class Str1(LdrStrBase):
397 opcode = 0b010 403 opcode = 0b010
398 bit20 = 0 404 bit20 = 0
399 mnemonic = 'STR' 405 mnemonic = 'STR'
400 406
401 407
402 class Ldr1(LdrStrBase): 408 class Ldr1(LdrStrBase):
403 opcode = 0b010 409 opcode = 0b010
404 bit20 = 1 410 bit20 = 1
405 mnemonic = 'LDR' 411 mnemonic = 'LDR'
412
413
414 class Adr(ArmInstruction):
415 def __init__(self, rd, label):
416 super().__init__()
417 self.rd = rd
418 self.label = label
419
420 def __repr__(self):
421 return 'ADR {}, {}'.format(self.rd, self.label)
422
423 def relocations(self):
424 return [(self.label, 'adr_imm12')]
425
426 def encode(self):
427 self.token.cond = AL
428 self.token[0:12] = 0 # Filled by linker
429 self.token[12:16] = self.rd.num
430 self.token[16:20] = 0b1111
431 self.token[25] = 1
432 return self.token.encode()
406 433
407 434
408 class Ldr3(ArmInstruction): 435 class Ldr3(ArmInstruction):
409 """ Load PC relative constant value 436 """ Load PC relative constant value
410 LDR rt, label 437 LDR rt, label