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comparison test/testasm.py @ 292:534b94b40aa8

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Fixup reorganize
author Windel Bouwman
date Wed, 27 Nov 2013 08:06:42 +0100
parents 7b38782ed496
children e84047f29c78
comparison
equal deleted inserted replaced
290:7b38782ed496 292:534b94b40aa8
2 2
3 import unittest, cProfile 3 import unittest, cProfile
4 from ppci import CompilerError 4 from ppci import CompilerError
5 from asmnodes import AInstruction, ABinop, AUnop, ASymbol, ALabel, ANumber 5 from asmnodes import AInstruction, ABinop, AUnop, ASymbol, ALabel, ANumber
6 from asm import tokenize, Assembler 6 from asm import tokenize, Assembler
7 import target.armtarget as arm
8 import outstream 7 import outstream
9 from target import Label 8 from target import Label
10 9
11 10
12 class AssemblerLexingCase(unittest.TestCase): 11 class AssemblerLexingCase(unittest.TestCase):
81 80
82 def testParse6(self): 81 def testParse6(self):
83 # A line can be empty 82 # A line can be empty
84 self.a.parse_line('') 83 self.a.parse_line('')
85 84
85
86 class AssemblerOtherTestCase(unittest.TestCase): 86 class AssemblerOtherTestCase(unittest.TestCase):
87 def testWithoutTarget(self): 87 def testWithoutTarget(self):
88 a = Assembler() 88 a = Assembler()
89 with self.assertRaises(CompilerError): 89 with self.assertRaises(CompilerError):
90 a.assemble_line('') 90 a.assemble_line('')
91
92 @unittest.skip
93 def testX86(self):
94 testsrc = """ ; tst
95 begin:
96 mov rax, rbx ; 0x48, 0x89, 0xd8
97 xor rcx, rbx ; 0x48, 0x31, 0xd9
98 inc rcx ; 0x48 0xff 0xc1
99 """
100 a = Assembler()
101 a.assemble(testsrc)
102 # Compare with nasm output:
103 nasmbytes = [0x48, 0x89, 0xd8, 0x48, 0x31, 0xd9, 0x48, 0xff, 0xc1]
104 91
105 92
106 class OustreamTestCase(unittest.TestCase): 93 class OustreamTestCase(unittest.TestCase):
107 def test1(self): 94 def test1(self):
108 o = outstream.BinOutputStream() 95 o = outstream.BinOutputStream()
110 o.emit(Label('a')) 97 o.emit(Label('a'))
111 self.assertSequenceEqual(bytes(), o.Data) 98 self.assertSequenceEqual(bytes(), o.Data)
112 99
113 100
114 class AsmTestCaseBase(unittest.TestCase): 101 class AsmTestCaseBase(unittest.TestCase):
102 """ Base testcase for assembly """
115 def feed(self, line): 103 def feed(self, line):
116 self.a.assemble(line) 104 self.a.assemble(line)
117 105
118 def check(self, hexstr): 106 def check(self, hexstr):
119 self.assertSequenceEqual(bytes.fromhex(hexstr), self.o.Data) 107 self.assertSequenceEqual(bytes.fromhex(hexstr), self.o.Data)
120 108
121 109
122 class AssemblerMSP430TestCase(AsmTestCaseBase):
123 def setUp(self):
124 self.t = msp430.msp430target
125 self.o = outstream.BinOutputStream()
126 self.o.selectSection('.text')
127 self.a = Assembler(target=self.t, stream=self.o)
128
129 def testMapMovInstruction(self):
130 i = AInstruction('mov', [ASymbol('r14'), ASymbol('r15')])
131 ri = self.t.mapInstruction(i)
132
133 def testMapRetiInstruction(self):
134 i = AInstruction('reti', [])
135 ri = self.t.mapInstruction(i)
136
137 @unittest.skip
138 def testMapOperand(self):
139 o = ASymbol('r14')
140 mo = self.t.mapOperand(o)
141 self.assertEqual(mo, msp430.r14)
142
143 @unittest.skip
144 def testMapOperandIndirection(self):
145 o = AUnop('[]', ASymbol('r14'))
146 mo = self.t.mapOperand(o)
147
148 def testMov(self):
149 line1 = "mov r14, r15"
150 self.feed(line1)
151 self.check('0F4E')
152
153 def testMov1337(self):
154 line1 = "mov 0x1337, r12"
155 self.feed(line1)
156 self.check('3C403713')
157
158 def testAdd(self):
159 line1 = "add r15, r13"
160 self.feed(line1)
161 self.check('0D5F')
162
163 def testReti(self):
164 line1 = "reti"
165 self.feed(line1)
166 self.check('0013')
167
168 def testMSPinstructionCount(self):
169 """ Check that there are 27 instructions """
170 self.assertEqual(27, len(self.t.instructions))
171
172
173 class AssemblerARMTestCase(AsmTestCaseBase):
174 def setUp(self):
175 self.t = arm.armtarget
176 self.o = outstream.BinOutputStream()
177 self.o.selectSection('.text')
178 self.a = Assembler(target=self.t, stream=self.o)
179
180 def testMapOperand(self):
181 pass
182
183 def testMovImm8(self):
184 self.feed('mov r4, 100')
185 self.check('6424')
186
187 @unittest.skip
188 def testMovExt(self):
189 self.feed('mov r3, sp')
190 self.check('')
191
192 def testYield(self):
193 self.feed('yield')
194 self.check('10bf')
195
196 def testPush(self):
197 self.feed('push {r2,r3,lr}')
198 self.check('0cb5')
199
200 def testPop(self):
201 self.feed('pop {r4-r6, pc}')
202 self.check('70bd')
203
204 def testStr5(self):
205 self.feed('str r4, [r1 + 0]')
206 self.check('0c60')
207
208 def testLdr5(self):
209 self.feed('ldr r4, [r0 + 0]')
210 self.check('0468')
211
212 def testLdrSpRel(self):
213 self.feed('ldr r0, [sp + 4]')
214 self.check('0198')
215
216 def testStrSpRel(self):
217 self.feed('str r0, [sp + 4]')
218 self.check('0190')
219
220 def testLdrPcRel(self):
221 self.feed('ldr r7, henkie')
222 self.feed('ldr r6, henkie')
223 self.feed('ldr r1, henkie')
224 self.feed('align 4')
225 self.feed('dcd 1')
226 self.feed('henkie: dcd 2')
227 self.check('024F024E 01490000 01000000 02000000')
228
229 def testBranch(self):
230 self.feed('start: b henkie')
231 self.feed('beq henkie')
232 self.feed('bne henkie')
233 self.feed('henkie: b start')
234 self.feed('eof: b eof')
235 self.check('01e000d0 ffd1fbe7 fee7')
236
237 def testConditions(self):
238 self.feed('blt x')
239 self.feed('bgt x')
240 self.feed('x:')
241 self.check('00dbffdc')
242
243 def testBoff(self):
244 self.feed('b henkie')
245 self.feed('b henkie')
246 self.feed('b henkie')
247 self.feed('b henkie')
248 self.feed('b henkie')
249 self.feed('b henkie')
250 self.feed('b henkie')
251 self.feed('henkie:')
252 self.feed('b henkie')
253 self.feed('b henkie')
254 self.feed('b henkie')
255 self.feed('b henkie')
256 self.check('05e004e0 03e002e0 01e000e0 ffe7fee7 fde7fce7 fbe7')
257
258 def testBl(self):
259 self.feed('bl henkie')
260 self.feed('bl henkie')
261 self.feed('henkie:')
262 self.feed('bl henkie')
263 self.feed('bl henkie')
264 self.check('00f0 02f8 00f0 00f8 fff7 feff fff7 fcff')
265
266 def testCmpRegReg(self):
267 self.feed('cmp r0, r1')
268 self.check('8842')
269
270 def testAddimm3(self):
271 self.feed('add r3, r5, 2')
272 self.feed('add r4, r1, 6')
273 self.check('ab1c8c1d')
274
275 def testSubImm3(self):
276 self.feed('sub r3, r5, 2')
277 self.feed('sub r4, r1, 6')
278 self.check('ab1e8c1f')
279
280 def testLeftShift(self):
281 self.feed('lsl r3, r5')
282 self.check('ab40')
283
284 def testAddSp(self):
285 self.feed('add sp,sp,8')
286 self.feed('add sp,sp,16')
287 self.check('02b004b0')
288
289 def testSubSp(self):
290 self.feed('sub sp,sp,32')
291 self.feed('sub sp,sp,4')
292 self.check('88b081b0')
293
294 def testSequence1(self):
295 self.feed('mov r5, 3')
296 self.feed('add r4, r5, 0')
297 self.feed('loop: add r6, r4, 7')
298 self.feed('cmp r6, 5')
299 self.check('0325 2c1c e61d 052e')
300
301 def testSequence2(self):
302 self.feed('henkie:')
303 self.feed('push {r1,r4,r5}')
304 self.feed('add r5, r2, r4')
305 self.feed('cmp r4, r2')
306 self.feed('ldr r0, [sp + 4]')
307 self.feed('str r3, [sp + 16]')
308 self.feed('pop {r1, r4, r5}')
309 self.feed('lsl r3, r4')
310 self.feed('cmp r3, r5')
311 self.feed('beq henkie')
312 self.feed('bne henkie')
313 self.feed('b henkie')
314 self.check('32b41519 94420198 049332bc a340ab42 f6d0f5d1 f4e7')
315
316 if __name__ == '__main__': 110 if __name__ == '__main__':
317 unittest.main() 111 unittest.main()