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comparison python/target/armregisters.py @ 341:4d204f6f7d4e devel

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Rewrite of assembler parts
author Windel Bouwman
date Fri, 28 Feb 2014 18:07:14 +0100
parents c7cc54c0dfdf
children
comparison
equal deleted inserted replaced
340:c7cc54c0dfdf 341:4d204f6f7d4e
15 15
16 16
17 class Reg16Op(ArmRegister): 17 class Reg16Op(ArmRegister):
18 pass 18 pass
19 19
20 def get_register(n):
21 for x in registers:
22 if x.num == n:
23 return x
24 raise Exception()
25
26 def register_range(a, b):
27 """ Return set of registers from a to b """
28 assert a.num < b.num
29 return {get_register(n) for n in range(a.num, b.num + 1)}
30
20 31
21 R0 = Reg8Op(0, 'r0') 32 R0 = Reg8Op(0, 'r0')
22 R1 = Reg8Op(1, 'r1') 33 R1 = Reg8Op(1, 'r1')
23 R2 = Reg8Op(2, 'r2') 34 R2 = Reg8Op(2, 'r2')
24 R3 = Reg8Op(3, 'r3') 35 R3 = Reg8Op(3, 'r3')
25 R4 = Reg8Op(4, 'r4') 36 R4 = Reg8Op(4, 'r4')
26 R5 = Reg8Op(5, 'r5') 37 R5 = Reg8Op(5, 'r5')
27 R6 = Reg8Op(6, 'r6') 38 R6 = Reg8Op(6, 'r6')
28 R7 = Reg8Op(7, 'r7') 39 R7 = Reg8Op(7, 'r7')
29 R7 = Reg8Op(8, 'r8') 40 R8 = Reg8Op(8, 'r8')
30 R7 = Reg8Op(9, 'r9') 41 R9 = Reg8Op(9, 'r9')
31 R7 = Reg8Op(10, 'r10') 42 R10 = Reg8Op(10, 'r10')
32 R7 = Reg8Op(11, 'r11') 43 R11 = Reg8Op(11, 'r11')
33 R7 = Reg8Op(12, 'r12') 44 R12 = Reg8Op(12, 'r12')
34 45
35 # Other registers: 46 # Other registers:
36 # TODO 47 # TODO
37 SP = ArmRegister(13, 'sp') 48 SP = ArmRegister(13, 'sp')
38 LR = ArmRegister(14, 'lr') 49 LR = ArmRegister(14, 'lr')