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comparison python/codegenarm.py @ 261:444b9df2ed99

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try to split up code generation
author Windel Bouwman
date Fri, 09 Aug 2013 09:05:13 +0200
parents ac603eb66b63
children ed14e077124c
comparison
equal deleted inserted replaced
260:b2f94b4951f1 261:444b9df2ed99
1 import logging 1 import logging
2 import ir 2 import ir
3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo 3 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
4 import cortexm3 as arm 4 import cortexm3 as arm
5 from ppci import CompilerError 5 from ppci import CompilerError
6 import irmach
6 7
7 class ArmCodeGenerator: 8 class ArmCodeGenerator:
8 """ 9 """
9 Simple code generator 10 Simple code generator
10 Ad hoc implementation 11 Ad hoc implementation
17 self.outs.emit(item) 18 self.outs.emit(item)
18 19
19 def generate(self, ircode): 20 def generate(self, ircode):
20 assert isinstance(ircode, ir.Module) 21 assert isinstance(ircode, ir.Module)
21 self.logger.info('Generating arm code for {}'.format(ircode.name)) 22 self.logger.info('Generating arm code for {}'.format(ircode.name))
22 self.available_regs = {arm.r2, arm.r3, arm.r4, arm.r5, arm.r6, arm.r7} 23 self.available_regs = {arm.r3, arm.r4, arm.r5, arm.r6, arm.r7}
23 self.regmap = {} 24 self.regmap = {}
24 # TODO: get these from linker descriptor? 25 # TODO: get these from linker descriptor?
25 self.outs.getSection('code').address = 0x08000000 26 self.outs.getSection('code').address = 0x08000000
26 self.outs.getSection('data').address = 0x20000000 27 self.outs.getSection('data').address = 0x20000000
27 self.outs.selectSection('data') 28 self.outs.selectSection('data')
49 pass #self.imms.append(( 50 pass #self.imms.append((
50 51
51 self.stack_frame = [] 52 self.stack_frame = []
52 self.emit(Label(f.name)) 53 self.emit(Label(f.name))
53 # Save some registers: 54 # Save some registers:
54 self.emit(arm.push_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6,arm.r7,arm.lr}))) 55 self.emit(arm.push_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
55 for bb in f.BasicBlocks: 56 for bb in f.BasicBlocks:
56 self.emit(Label(bb.name)) 57 self.emit(Label(bb.name))
57 for ins in bb.Instructions: 58 for ins in bb.Instructions:
58 self.generateInstruction(ins) 59 self.generateInstruction(ins)
59 60
165 self.freereg(ins.value2, ins) 166 self.freereg(ins.value2, ins)
166 elif type(ins) is ir.Call: 167 elif type(ins) is ir.Call:
167 # TODO: prep parameters: 168 # TODO: prep parameters:
168 self.emit(arm.bl_ins(LabelRef(ins.callee.name))) 169 self.emit(arm.bl_ins(LabelRef(ins.callee.name)))
169 elif type(ins) is ir.Return: 170 elif type(ins) is ir.Return:
170 self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc}))) 171 self.emit(arm.pop_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
171 elif type(ins) is ir.ConditionalBranch: 172 elif type(ins) is ir.ConditionalBranch:
172 r0 = self.getreg(ins.a) 173 r0 = self.getreg(ins.a)
173 r1 = self.getreg(ins.b) 174 r1 = self.getreg(ins.b)
174 self.emit(arm.cmp_ins(r1, r0)) 175 self.emit(arm.cmp_ins(r1, r0))
175 tgt_yes = Label(ins.lab1.name) 176 tgt_yes = Label(ins.lab1.name)