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comparison python/cortexm3.py @ 258:04c19282a5aa

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Added register allocator
author Windel Bouwman
date Mon, 05 Aug 2013 19:46:11 +0200
parents 6ed3d3a82a63
children 444b9df2ed99
comparison
equal deleted inserted replaced
257:703321743e8a 258:04c19282a5aa
339 return u16(h) 339 return u16(h)
340 def __repr__(self): 340 def __repr__(self):
341 return 'MOV {0}, xx?'.format(self.r) 341 return 'MOV {0}, xx?'.format(self.r)
342 342
343 343
344 @armtarget.instruction
345 class movregreg_ins(ArmInstruction):
346 """ mov Rd, Rm """
347 mnemonic = 'mov'
348 operands = (Reg8Op, Reg8Op)
349 def __init__(self, rd, rm):
350 self.rd = rd
351 self.rm = rm
352 def encode(self):
353 rd = self.rd.num
354 rm = self.rm.num
355 h = 0 | (rm << 3) | rd
356 return u16(h)
357 344
358 345
359 346
360 # Arithmatics: 347 # Arithmatics:
361 348
417 return u16(h) 404 return u16(h)
418 def __repr__(self): 405 def __repr__(self):
419 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm) 406 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
420 407
421 @armtarget.instruction 408 @armtarget.instruction
409 class movregreg_ins(regreg_base):
410 """ mov Rd, Rm """
411 mnemonic = 'mov'
412 opcode = 0
413
414 @armtarget.instruction
422 class andregs_ins(regreg_base): 415 class andregs_ins(regreg_base):
423 mnemonic = 'AND' 416 mnemonic = 'AND'
424 opcode = 0b0100000000 417 opcode = 0b0100000000
425 418
426 @armtarget.instruction 419 @armtarget.instruction