annotate python/arm_cm3.py @ 202:f22b431f4113

Added arm add instruction
author Windel Bouwman
date Sat, 15 Jun 2013 10:02:50 +0200
parents
children ca1ea402f6a1
rev   line source
202
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
1 from target import Register, Instruction, Target
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
2 from asmnodes import ASymbol, ANumber
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
3 from ppci import CompilerError
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
4 import struct, types
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
5
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
6 def u16(h):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
7 return struct.pack('<H', h)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
8
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
9 armtarget = Target('arm')
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
10
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
11 # Add a custom operand mapping method:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
12 def mapOp(self, operand):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
13 if type(operand) is ASymbol:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
14 # try to map to register:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
15 regs = {}
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
16 for r in self.registers:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
17 regs[r.name] = r
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
18 if operand.name in regs:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
19 reg = regs[operand.name]
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
20 return reg
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
21 elif type(operand) is ANumber:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
22 return ArmImm(operand.number)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
23 raise CompilerError('Cannot map {0}'.format(operand))
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
24
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
25 armtarget.mapOperand = types.MethodType(mapOp, armtarget)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
26
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
27 # Define:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
28 registers = 'r0,r1,r2,r3,r4,r5'
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
29
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
30 class ArmReg(Register):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
31 def __init__(self, num, name):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
32 super().__init__(name)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
33 self.num = num
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
34
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
35 class ArmImm:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
36 def __init__(self, i):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
37 self.i = i
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
38
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
39 # 8 bit registers:
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
40 r4 = ArmReg(4, 'r4')
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
41 armtarget.registers.append(r4)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
42
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
43 class ArmInstruction(Instruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
44 pass
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
45
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
46 @armtarget.instruction
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
47 class ldr_ins(ArmInstruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
48 mnemonic = 'ldr'
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
49 opcode = 1337
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
50
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
51
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
52 @armtarget.instruction
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
53 class mov_ins(ArmInstruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
54 """ mov Rd, imm8, move immediate value into register """
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
55 mnemonic = 'mov'
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
56 opcode = 4 # 00100
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
57 operands = (ArmReg, ArmImm)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
58 def __init__(self, r, imm):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
59 self.imm = imm.i
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
60 self.r = r.num
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
61 def encode(self):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
62 rd = self.r
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
63 opcode = self.opcode
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
64 imm8 = self.imm
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
65 h = (opcode << 11) | (rd << 8) | imm8
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
66 return u16(h)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
67
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
68
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
69 @armtarget.instruction
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
70 class yield_ins(ArmInstruction):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
71 operands = ()
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
72 mnemonic = 'yield'
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
73 def encode(self):
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
74 return u16(0xbf10)
f22b431f4113 Added arm add instruction
Windel Bouwman
parents:
diff changeset
75