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202
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1 from target import Register, Instruction, Target
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2 from asmnodes import ASymbol, ANumber
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3 from ppci import CompilerError
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4 import struct, types
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5
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6 def u16(h):
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7 return struct.pack('<H', h)
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8
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9 armtarget = Target('arm')
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10
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11 class ArmReg(Register):
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12 def __init__(self, num, name):
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13 super().__init__(name)
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14 self.num = num
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15
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16 class ArmImm:
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17 def __init__(self, i):
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18 self.i = i
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19
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203
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20 class RegOp:
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21 def __init__(self, num):
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22 assert num < 8
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23 self.num = num
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24
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25 @classmethod
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26 def Create(cls, vop):
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27 if type(vop) is ASymbol:
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28 name = vop.name
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29 regs = {}
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30 for r in armtarget.registers:
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31 regs[r.name] = r
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32 if name in regs:
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33 r = regs[name]
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34 return cls(r.num)
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35
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36 class Imm8:
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37 def __init__(self, imm):
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38 assert imm < 256
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39 self.imm = imm
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40
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41 @classmethod
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42 def Create(cls, vop):
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43 if type(vop) is ANumber and vop.number < 256:
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44 return cls(vop.number)
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45
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46 class Imm3:
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47 def __init__(self, imm):
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48 assert imm < 8
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49 assert type(imm) is int
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50 self.imm = imm
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51
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52 @classmethod
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53 def Create(cls, vop):
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54 if type(vop) is ANumber and vop.number < 8:
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55 return cls(vop.number)
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56
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202
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57 # 8 bit registers:
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58 r4 = ArmReg(4, 'r4')
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59 armtarget.registers.append(r4)
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203
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60 r5 = ArmReg(5, 'r5')
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61 armtarget.registers.append(r5)
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62 r6 = ArmReg(6, 'r6')
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63 armtarget.registers.append(r6)
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64 r7 = ArmReg(7, 'r7')
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65 armtarget.registers.append(r7)
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202
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66
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67 class ArmInstruction(Instruction):
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68 pass
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69
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70 @armtarget.instruction
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71 class ldr_ins(ArmInstruction):
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72 mnemonic = 'ldr'
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73 opcode = 1337
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74
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75
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203
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76 class Operand2:
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77 def __init__(self, expr):
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78 if type(expr) is ANumber:
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79 pass
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80 pass
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81
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202
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82 @armtarget.instruction
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83 class mov_ins(ArmInstruction):
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84 """ mov Rd, imm8, move immediate value into register """
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85 mnemonic = 'mov'
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203
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86 opcode = 4 # 00100 Rd(3) imm8
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87 operands = (RegOp, Imm8)
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88 def __init__(self, rd, imm):
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89 self.imm = imm.imm
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90 self.r = rd.num
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202
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91 def encode(self):
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92 rd = self.r
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93 opcode = self.opcode
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94 imm8 = self.imm
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95 h = (opcode << 11) | (rd << 8) | imm8
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96 return u16(h)
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97
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203
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98 @armtarget.instruction
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99 class movregreg_ins(ArmInstruction):
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100 """ mov Rd, Rm """
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101 mnemonic = 'mov'
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102 opcode = 8 # 01000 Rd(3) imm8
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103 operands = (RegOp, RegOp)
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104 def __init__(self, rd, rm):
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105 self.rd = rd
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106 self.rm = rm
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107 def encode(self):
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108 rd = self.rd.num
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109 D = (rd & 0x8) >> 3
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110 assert D < 2
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111 rd = rd & 0x7
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112 rm = self.rm.num
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113 assert rm < 16
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114 opcode = self.opcode
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115 h = (opcode << 11) | (3 << 9) | (D << 7) | (rm << 3) | rd
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116 return u16(h)
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117
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118 @armtarget.instruction
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119 class addregregimm3_ins(ArmInstruction):
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120 """ add Rd, Rn, imm3 """
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121 mnemonic = 'add'
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122 opcode = 3 # 00011
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123 operands = (RegOp, RegOp, Imm3)
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124 def __init__(self, rd, rn, imm3):
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125 self.rd = rd
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126 self.rn = rn
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127 self.imm3 = imm3
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128 def encode(self):
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129 rd = self.rd.num
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130 rn = self.rn.num
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131 imm3 = self.imm3.imm
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132 opcode = self.opcode
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133 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
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134 return u16(h)
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135
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136 @armtarget.instruction
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137 class cmpregimm8_ins(ArmInstruction):
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138 """ cmp Rn, imm8 """
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139 mnemonic = 'cmp'
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140 opcode = 5 # 00101
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141 operands = (RegOp, Imm8)
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142 def __init__(self, rn, imm):
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143 self.rn = rn
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144 self.imm = imm
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145 def encode(self):
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146 rn = self.rn.num
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147 imm = self.imm.imm
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148 opcode = self.opcode
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149 h = (opcode << 11) | (rn << 8) | imm
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150 return u16(h)
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202
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151
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152 @armtarget.instruction
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153 class yield_ins(ArmInstruction):
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154 operands = ()
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155 mnemonic = 'yield'
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156 def encode(self):
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157 return u16(0xbf10)
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158
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