annotate ide/compiler/assembler.py @ 33:d8185ddb6c7b

Added more interrupt handlers
author windel
date Sun, 15 Jan 2012 13:39:49 +0100
parents 92df07bc2081
children
rev   line source
1
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1 """
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2 Assembler code generation functions
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3 """
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4
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5 from .errors import Error
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6
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7 modrm = {'rax': 0, 'rbx': 1}
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8
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9 # Table 3.1 of the intel manual:
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10 # use REX.W on the table below:
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11 regs64 = {'rax': 0,'rcx':1,'rdx':2,'rbx':3,'rsp':4,'rbp':5,'rsi':6,'rdi':7,'r8':0,'r9':1,'r10':2,'r11':3,'r12':4,'r13':5,'r14':6,'r15':7}
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12 regs32 = {'eax': 0, 'ecx':1, 'edx':2, 'ebx': 3, 'esp': 4, 'ebp': 5, 'esi':6, 'edi':7}
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13 regs8 = {'al':0,'cl':1,'dl':2,'bl':3,'ah':4,'ch':5,'dh':6,'bh':7}
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14
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15 # Calculation of the rexb bit:
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16 rexbit = {'rax': 0, 'rcx':0, 'rdx':0, 'rbx': 0, 'rsp': 0, 'rbp': 0, 'rsi':0, 'rdi':0,'r8':1,'r9':1,'r10':1,'r11':1,'r12':1,'r13':1,'r14':1,'r15':1}
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17
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18 # Helper functions:
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19 def imm64(x):
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20 """ represent 64 bits integer in little endian 8 bytes"""
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21 if x < 0:
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22 x = x + (1 << 64)
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23 x = x & 0xFFFFFFFFFFFFFFFF
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24 return [ (x >> (p*8)) & 0xFF for p in range(8) ]
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25
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26 def imm32(x):
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27 """ represent 32 bits integer in little endian 4 bytes"""
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28 if x < 0:
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29 x = x + (1 << 32)
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30 x = x & 0xFFFFFFFF
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31 return [ (x >> (p*8)) & 0xFF for p in range(4) ]
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32
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33 def imm8(x):
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34 if x < 0:
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35 x = x + (1 << 8)
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36 x = x & 0xFF
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37 return [ x ]
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38
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39 def modrm(mod=0, rm=0, reg=0):
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40 """ Construct the modrm byte from its components """
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41 assert(mod <= 3)
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42 assert(rm <= 7)
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43 assert(reg <= 7)
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44 return (mod << 6) | (reg << 3) | rm
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45
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46 def rex(w=0, r=0, x=0, b=0):
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47 """ Create a REX prefix byte """
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48 assert(w <= 1)
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49 assert(r <= 1)
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50 assert(x <= 1)
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51 assert(b <= 1)
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52 return 0x40 | (w<<3) | (r<<2) | (x<<1) | b
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53
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54 def sib(ss=0, index=0, base=0):
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55 assert(ss <= 3)
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56 assert(index <= 7)
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57 assert(base <= 7)
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58 return (ss << 6) | (index << 3) | base
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59
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60 tttn = {'L':0xc,'G':0xf,'NE':0x5,'GE':0xd,'LE':0xe, 'E':0x4}
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61
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62 # Actual instructions:
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63 def nearjump(distance, condition=None):
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64 """ jmp imm32 """
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65 lim = (1<<30)
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66 if abs(distance) > lim:
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67 Error('near jump cannot jump over more than {0} bytes'.format(lim))
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68 if condition:
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69 if distance < 0:
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70 distance -= 6 # Skip own instruction
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71 opcode = 0x80 | tttn[condition] # Jcc imm32
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72 return [0x0F, opcode] + imm32(distance)
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73 else:
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74 if distance < 0:
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75 distance -= 5 # Skip own instruction
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76 return [ 0xE9 ] + imm32(distance)
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77
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78 def shortjump(distance, condition=None):
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79 """ jmp imm8 """
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80 lim = 118
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81 if abs(distance) > lim:
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82 Error('short jump cannot jump over more than {0} bytes'.format(lim))
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83 if distance < 0:
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84 distance -= 2 # Skip own instruction
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85 if condition:
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86 opcode = 0x70 | tttn[condition] # Jcc rel8
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87 else:
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88 opcode = 0xeb # jmp rel8
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89 return [opcode] + imm8(distance)
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90
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91 # Helper that determines jump type:
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92 def reljump(distance):
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93 if abs(distance) < 110:
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94 return shortjump(distance)
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95 else:
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96 return nearjump(distance)
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97
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98 def push(reg):
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99 if reg in regs64:
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100 if rexbit[reg] == 1:
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101 return [0x41, 0x50 + regs64[reg]]
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102 else:
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103 return [0x50 + regs64[reg]]
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104 else:
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105 Error('push for {0} not implemented'.format(reg))
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106
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107 def pop(reg):
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108 if reg in regs64:
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109 if rexbit[reg] == 1:
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110 rexprefix = rex(b=1)
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111 opcode = 0x58 + regs64[reg]
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112 return [rexprefix, opcode]
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113 else:
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114 opcode = 0x58 + regs64[reg]
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115 return [ opcode ]
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116 else:
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117 Error('pop for {0} not implemented'.format(reg))
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118
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119 def INT(number):
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120 opcode = 0xcd
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121 return [opcode] + imm8(number)
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122
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123 def syscall():
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124 return [0x0F, 0x05]
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125
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126 def call(distance):
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127 if type(distance) is int:
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128 return [0xe8]+imm32(distance)
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129 elif type(distance) is str and distance in regs64:
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130 reg = distance
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131 opcode = 0xFF # 0xFF /2 == call r/m64
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132 mod_rm = modrm(mod=3, reg=2, rm=regs64[reg])
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133 if rexbit[reg] == 1:
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134 rexprefix = rex(b=rexbit[reg])
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135 return [rexprefix, opcode, mod_rm]
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136 else:
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137 return [opcode, mod_rm]
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138 else:
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139 Error('Cannot call to {0}'.format(distance))
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140
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141 def ret():
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142 return [ 0xc3 ]
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143
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144 def increg64(reg):
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145 assert(reg in regs64)
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146 rexprefix = rex(w=1, b=rexbit[reg])
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147 opcode = 0xff
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148 mod_rm = modrm(mod=3, rm=regs64[reg])
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149 return [rexprefix, opcode, mod_rm]
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150
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151 def prepost8(r8, rm8):
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152 assert(r8 in regs8)
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153 pre = []
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154 if type(rm8) is list:
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155 # TODO: merge mem access with prepost for 64 bits
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156 if len(rm8) == 1:
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157 base, = rm8
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158 if type(base) is str and base in regs64:
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159 assert(not base in ['rbp', 'rsp', 'r12', 'r13'])
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160 mod_rm = modrm(mod=0, rm=regs64[base], reg=regs8[r8])
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161 if rexbit[base] == 1:
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162 pre.append(rex(b=1))
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163 post = [mod_rm]
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164 else:
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165 Error('One arg of type {0} not implemented'.format(base))
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166 elif len(rm8) == 2:
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167 base, offset = rm8
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168 assert(type(offset) is int)
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169 assert(base in regs64)
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170
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171 if base == 'rsp' or base == 'r12':
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172 Error('Cannot use rsp or r12 as base yet')
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173 if rexbit[base] == 1:
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174 pre.append( rex(b=1) )
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175 mod_rm = modrm(mod=1, rm=regs64[base], reg=regs8[r8])
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176 post = [mod_rm] + imm8(offset)
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177 else:
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178 Error('not supporting prepost8 with list len {0}'.format(len(rm8)))
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179 else:
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180 Error('Not supporting move with reg8 {0}'.format(r8))
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181 return pre, post
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182
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183 def prepost(r64, rm64):
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184 assert(r64 in regs64)
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185 if type(rm64) is list:
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186 if len(rm64) == 3:
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187 base, index, disp = rm64
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188 assert(base in regs64)
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189 assert(index in regs64)
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190 assert(type(disp) is int)
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191 # Assert that no special cases are used:
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192 # TODO: swap base and index to avoid special cases
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193 # TODO: exploit special cases and make better code
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194 assert(index != 'rsp')
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195
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196 rexprefix = rex(w=1, r=rexbit[r64], x=rexbit[index], b=rexbit[base])
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197 # mod=1 and rm=4 indicates a SIB byte: [--][--]+imm8
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198 mod_rm = modrm(mod=1, rm=4, reg=regs64[r64])
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199 si_b = sib(ss=0, index=regs64[index], base=regs64[base])
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200 return [rexprefix], [mod_rm, si_b] + imm8(disp)
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201 elif len(rm64) == 2:
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202 base, offset = rm64
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203 assert(type(offset) is int)
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204 if base == 'RIP':
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205 # RIP pointer relative addressing mode!
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206 rexprefix = rex(w=1, r=rexbit[r64])
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207 mod_rm = modrm(mod=0, rm=5, reg=regs64[r64])
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208 return [rexprefix], [mod_rm] + imm32(offset)
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209 else:
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210 assert(base in regs64)
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211
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212 if base == 'rsp' or base == 'r12':
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213 # extended function that uses SIB byte
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214 rexprefix = rex(w=1, r=rexbit[r64], b=rexbit[base])
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215 # rm=4 indicates a SIB byte follows
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
216 mod_rm = modrm(mod=1, rm=4, reg=regs64[r64])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
217 # index=4 indicates that index is not used
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
218 si_b = sib(ss=0, index=4, base=regs64[base])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
219 return [rexprefix], [mod_rm, si_b] + imm8(offset)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
220 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
221 rexprefix = rex(w=1, r=rexbit[r64], b=rexbit[base])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
222 mod_rm = modrm(mod=1, rm=regs64[base], reg=regs64[r64])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
223 return [rexprefix], [mod_rm] + imm8(offset)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
224 elif len(rm64) == 1:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
225 offset = rm64[0]
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
226 if type(offset) is int:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
227 rexprefix = rex(w=1, r=rexbit[r64])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
228 mod_rm = modrm(mod=0, rm=4,reg=regs64[r64])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
229 si_b = sib(ss=0, index=4,base=5) # 0x25
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
230 return [rexprefix], [mod_rm, si_b] + imm32(offset)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
231 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
232 Error('Memory reference of type {0} not implemented'.format(offset))
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
233 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
234 Error('Memory reference not implemented')
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
235 elif rm64 in regs64:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
236 rexprefix = rex(w=1, r=rexbit[r64], b=rexbit[rm64])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
237 mod_rm = modrm(3, rm=regs64[rm64], reg=regs64[r64])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
238 return [rexprefix], [mod_rm]
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
239
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
240 def leareg64(rega, m):
92df07bc2081 Initial import of compiler
windel
parents:
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241 opcode = 0x8d # lea r64, m
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
242 pre, post = prepost(rega, m)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
243 return pre + [opcode] + post
92df07bc2081 Initial import of compiler
windel
parents:
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244
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
245 def mov(rega, regb):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
246 if type(regb) is int:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
247 pre = [rex(w=1, b=rexbit[rega])]
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
248 opcode = 0xb8 + regs64[rega]
92df07bc2081 Initial import of compiler
windel
parents:
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249 post = imm64(regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
250 elif type(regb) is str:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
251 if regb in regs64:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
252 opcode = 0x89 # mov r/m64, r64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
253 pre, post = prepost(regb, rega)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
254 elif regb in regs8:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
255 opcode = 0x88 # mov r/m8, r8
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
256 pre, post = prepost8(regb, rega)
92df07bc2081 Initial import of compiler
windel
parents:
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257 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
258 Error('Unknown register {0}'.format(regb))
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
259 elif type(rega) is str:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
260 if rega in regs64:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
261 opcode = 0x8b # mov r64, r/m64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
262 pre, post = prepost(rega, regb)
92df07bc2081 Initial import of compiler
windel
parents:
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263 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
264 Error('Unknown register {0}'.format(rega))
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
265 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
266 Error('Move of this kind {0}, {1} not implemented'.format(rega, regb))
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
267 return pre + [opcode] + post
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
268
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
269 def xorreg64(rega, regb):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
270 rexprefix = rex(w=1, r=rexbit[regb], b=rexbit[rega])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
271 opcode = 0x31 # XOR r/m64, r64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
272 # Alternative is 0x33 XOR r64, r/m64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
273 mod_rm = modrm(3, rm=regs64[rega], reg=regs64[regb])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
274 return [rexprefix, opcode, mod_rm]
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
275
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
276 # integer arithmatic:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
277 def addreg64(rega, regb):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
278 if regb in regs64:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
279 pre, post = prepost(regb, rega)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
280 opcode = 0x01 # ADD r/m64, r64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
281 return pre + [opcode] + post
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
282 elif type(regb) is int:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
283 if regb < 100:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
284 rexprefix = rex(w=1, b=rexbit[rega])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
285 opcode = 0x83 # add r/m, imm8
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
286 mod_rm = modrm(3, rm=regs64[rega], reg=0)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
287 return [rexprefix, opcode, mod_rm]+imm8(regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
288 elif regb < (1<<31):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
289 rexprefix = rex(w=1, b=rexbit[rega])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
290 opcode = 0x81 # add r/m64, imm32
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
291 mod_rm = modrm(3, rm=regs64[rega], reg=0)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
292 return [rexprefix, opcode, mod_rm]+imm32(regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
293 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
294 Error('Constant value too large!')
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
295 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
296 Error('unknown second operand!'.format(regb))
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
297
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
298 def subreg64(rega, regb):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
299 if regb in regs64:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
300 pre, post = prepost(regb, rega)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
301 opcode = 0x29 # SUB r/m64, r64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
302 return pre + [opcode] + post
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
303 elif type(regb) is int:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
304 if regb < 100:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
305 rexprefix = rex(w=1, b=rexbit[rega])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
306 opcode = 0x83 # sub r/m, imm8
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
307 mod_rm = modrm(3, rm=regs64[rega], reg=5)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
308 return [rexprefix, opcode, mod_rm]+imm8(regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
309 elif regb < (1<<31):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
310 rexprefix = rex(w=1, b=rexbit[rega])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
311 opcode = 0x81 # sub r/m64, imm32
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
312 mod_rm = modrm(3, rm=regs64[rega], reg=5)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
313 return [rexprefix, opcode, mod_rm]+imm32(regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
314 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
315 Error('Constant value too large!')
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
316
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
317 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
318 Error('unknown second operand!'.format(regb))
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
319
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
320 def idivreg64(reg):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
321 rexprefix = rex(w=1, b=rexbit[reg])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
322 opcode = 0xf7 # IDIV r/m64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
323 mod_rm = modrm(3, rm=regs64[reg], reg=7)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
324 return [rexprefix, opcode, mod_rm]
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
325
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
326 def imulreg64_rax(reg):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
327 rexprefix = rex(w=1, b=rexbit[reg])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
328 opcode = 0xf7 # IMUL r/m64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
329 mod_rm = modrm(3, rm=regs64[reg], reg=5)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
330 return [rexprefix, opcode, mod_rm]
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
331
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
332 def imulreg64(rega, regb):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
333 pre, post = prepost(rega, regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
334 opcode = 0x0f # IMUL r64, r/m64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
335 opcode2 = 0xaf
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
336 return pre + [opcode, opcode2] + post
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
337
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
338 def cmpreg64(rega, regb):
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
339 if regb in regs64:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
340 pre, post = prepost(regb, rega)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
341 opcode = 0x39 # CMP r/m64, r64
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
342 return pre + [opcode] + post
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
343 elif type(regb) is int:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
344 rexprefix = rex(w=1, b=rexbit[rega])
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
345 opcode = 0x83 # CMP r/m64, imm8
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
346 mod_rm = modrm(3, rm=regs64[rega], reg=7)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
347 return [rexprefix, opcode, mod_rm] + imm8(regb)
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
348
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
349 else:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
350 Error('not implemented cmp64')
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
351
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
352 # Mapping that maps string names to the right functions:
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
353 opcodes = {'mov':(mov,2), 'lea':(leareg64,2), 'int':(INT,1), 'syscall':(syscall,0)}
92df07bc2081 Initial import of compiler
windel
parents:
diff changeset
354