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291
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1 from target import Register, Instruction, Target
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2
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3 class x86Register(Register):
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4 def __init__(self, name):
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5 self.name = name
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6
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7 class REG16(x86Register):
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8 pass
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9
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10 def addRegs(cls, names):
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11 for name in names:
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12 r = cls(name)
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13 globals()[name] = r
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14
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15 addRegs(REG16, ['ax', 'bx', 'cx'])
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16
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17 regs = """
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18 ax; reg16
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19 """
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20
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21 class MO:
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22 def __init__(self):
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23 pass
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24
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25 instrs = """
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26 add; 0x0; mem8/reg8; reg8
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27 """
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28
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29 # machine op table:
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30 mot = []
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31
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32 for i in instrs.split('\n'):
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33 i = i.strip()
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34 if i:
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35 print('INS:', i)
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36 mnemonic, opcode, op1, op2 = [a.strip() for a in i.split(';')]
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37 print(op1.split('/'), op2.split('/'))
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38
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39
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40 print(mot)
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41
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42 # Test first with these 3 instructions:
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43 """
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44 mov reg64, reg64 : opcode=0x89
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45 xor reg64, reg64 : opcode=0x31
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46 inc reg64 : opcode=0xff
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47 """
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48
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49 class x86Machine:
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50 def __init__(self):
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51 self.table = []
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52 self.table.append((0x0, 'add', 'reg8/mem8, reg8'))
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53 self.table.append((0x1, 'add', 'reg16/mem16/reg32/mem32, reg16/reg32'))
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54 self.table.append((0x2, 'add', 'reg8, reg8/mem8'))
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55 def forMnemonic(self, m):
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56 return [i for i in self.table if i[1] == m]
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57 def emit(self, m, ops):
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58 print(m, ops)
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59 ops = self.forMnemonic(m)
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60 print(ops)
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61
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62
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63 if __name__ == '__main__':
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64 m = x86Machine()
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65 m.emit('add', [ax, cx])
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66 m.emit('mov', [bx, 1337])
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