annotate python/target/arm.brg @ 336:d1ecc493384e

Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
author Windel Bouwman
date Wed, 19 Feb 2014 22:32:15 +0100
parents e9fe6988497c
children 4d204f6f7d4e
rev   line source
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
1
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
2 from target.basetarget import Label, Comment, Alignment, LabelRef, DebugInfo, Nop
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
3 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
4 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
5 from target.arminstructions import Mov2, Mov3
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
6 from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 323
diff changeset
7 from ppci import ir
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
8
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
9 %%
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
10
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
11 %terminal ADDI32 SUBI32 MULI32
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
12 %terminal ORI32 SHLI32
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
13 %terminal CONSTI32 MEMI32 REGI32 CALL
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
14 %terminal MOVI32
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
15
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
16 %%
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
17
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
18
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
19 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
20 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
21 reg: ORI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Orr, dst=[], src=[d, $2]); return d .)
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
22 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Lsl, dst=[], src=[d, $2]); return d .)
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
23 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Mul, dst=[d], src=[$2, d]); return d .)
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
24
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
25 reg: CONSTI32 3 (. d = self.newTmp(); ln = LabelRef(self.selector.frame.addConstant($$.value)); self.emit(Ldr3, dst=[d], others=[ln]); return d .)
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
26 reg: MEMI32(reg) 4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1], others=[0]); return d .)
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
27 reg: REGI32 1 (. return $$.value .)
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
28 reg: CALL 1 (. return self.selector.munchCall($$.value) .)
322
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
29
44f336460c2a Half of use of burg spec for arm
Windel Bouwman
parents:
diff changeset
30
323
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
31 stmt: MOVI32(MEMI32(addr), reg) 3 (. self.emit(Str2, src=[$1, $2]) .)
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
32
e9fe6988497c Used burg for generating expressions
Windel Bouwman
parents: 322
diff changeset
33 addr: reg 2 (. .)