398
|
1 """
|
|
2 Contains register definitions for x86 target.
|
|
3 """
|
|
4 from ..basetarget import Register
|
|
5
|
|
6
|
|
7 class X86Register(Register):
|
|
8 def __init__(self, num, name):
|
|
9 super().__init__(name)
|
|
10 self.num = num
|
|
11
|
|
12 def __repr__(self):
|
|
13 return 'x86reg {}'.format(self.name)
|
|
14
|
|
15 @property
|
|
16 def rexbit(self):
|
|
17 return (self.num >> 3) & 0x1
|
|
18
|
|
19 @property
|
|
20 def regbits(self):
|
|
21 return self.num & 0x7
|
|
22
|
|
23 # Calculation of the rexb bit:
|
|
24 # rexbit = {'rax': 0, 'rcx':0, 'rdx':0, 'rbx': 0, 'rsp': 0, 'rbp': 0, 'rsi':0,
|
|
25 # 'rdi':0,'r8':1,'r9':1,'r10':1,'r11':1,'r12':1,'r13':1,'r14':1,'r15':1}
|
|
26
|
|
27 # regs64 = {'rax': 0,'rcx':1,'rdx':2,'rbx':3,'rsp':4,'rbp':5,'rsi':6,'rdi':7,
|
|
28 # 'r8':0,'r9':1,'r10':2,'r11':3,'r12':4,'r13':5,'r14':6,'r15':7}
|
|
29 # regs32 = {'eax': 0, 'ecx':1, 'edx':2, 'ebx': 3, 'esp': 4, 'ebp': 5, 'esi':6,
|
|
30 # 'edi':7}
|
|
31 # regs8 = {'al':0,'cl':1,'dl':2,'bl':3,'ah':4,'ch':5,'dh':6,'bh':7}
|
|
32 rax = X86Register(0, 'rax')
|
|
33 rcx = X86Register(1, 'rcx')
|
|
34 rdx = X86Register(2, 'rdx')
|
|
35 rbx = X86Register(3, 'rbx')
|
|
36 rsp = X86Register(4, 'rsp')
|
|
37 rbp = X86Register(5, 'rbp')
|
|
38 rsi = X86Register(6, 'rsi')
|
|
39 rdi = X86Register(7, 'rdi')
|
|
40
|
|
41 r8 = X86Register(8, 'r8')
|
|
42 r9 = X86Register(9, 'r9')
|
|
43 r10 = X86Register(10, 'r10')
|
|
44 r11 = X86Register(11, 'r11')
|
|
45 r12 = X86Register(12, 'r12')
|
|
46 r13 = X86Register(13, 'r13')
|
|
47 r14 = X86Register(14, 'r14')
|
|
48 r15 = X86Register(15, 'r15')
|
|
49
|
|
50 low_regs = {rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi}
|
|
51
|
|
52 regs64 = {r8, r9, r10, r11, r12, r13, r14, r15} | low_regs
|