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2
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3 from ..basetarget import Instruction
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4
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5 from .token import ArmToken
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345
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6 from .registers import R0, SP, ArmRegister
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7
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8 # Helpers:
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9
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10 def rotate_right(v, n):
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11 """ bit-wise Rotate right n times """
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12 mask = (2**n) - 1
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13 mask_bits = v & mask
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14 return (v >> n) | (mask_bits << (32 - n))
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15
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16 def rotate_left(v, n):
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17 assert n >= 0
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18 assert n < 32
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19 return rotate_right(v, 32 - n)
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20
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21 masks = [rotate_right(0xFF, i * 2) for i in range(16)]
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22 #0x000000FF,
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23 #0xC000007F,
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24 #0xF000000F,
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25 #0xFC000003,
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26 #0xFF000000, # 4
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27
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28 assert masks[4] == 0xFF000000, hex(masks[4])
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29
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30 def encode_imm32(v):
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31 """ Bundle 32 bit value into 4 bits rotation and 8 bits value
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32 """
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33 for i in range(0, 16):
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34 v2 = rotate_left(v, i*2)
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35 if (v2 & 0xFFFFFF00) == 0:
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36 rotation = i
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37 val = v2 & 0xFF
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38 x = (rotation << 8) | val
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39 return x
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40 raise Exception("Invalid value {}".format(v))
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342
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41
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42 # Instructions:
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43
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44 class ArmInstruction(Instruction):
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45 def __init__(self):
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46 self.token = ArmToken()
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47
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48
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49 class Mov(ArmInstruction):
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50 """ Mov Rd, imm16 """
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51 def __init__(self, reg, imm):
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52 super().__init__()
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53 self.reg = reg
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54 self.imm = imm
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55
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56 def encode(self):
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57 self.token[0:12] = self.imm
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58 self.token.Rd = self.reg.num
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59 self.token[16:20] = 0
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60 self.token[20] = 0
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61 self.token[21:28] = 0b0011101
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62 self.token.cond = 0xE # Always!
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63 return self.token.encode()
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64
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65 def relocations(self):
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66 return []
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67
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68 def __repr__(self):
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345
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69 return 'Mov {}, {}'.format(self.reg, self.imm)
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70
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71
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72 def Add(*args):
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73 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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74 isinstance(args[1], ArmRegister):
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75 if isinstance(args[2], ArmRegister):
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76 return Add1(args[0], args[1], args[2])
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77 elif isinstance(args[2], int):
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78 return Add2(args[0], args[1], args[2])
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79 raise Exception()
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80
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81 def Sub(*args):
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82 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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83 isinstance(args[1], ArmRegister):
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84 if isinstance(args[2], ArmRegister):
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85 return Sub1(args[0], args[1], args[2])
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86 elif isinstance(args[2], int):
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87 return Sub2(args[0], args[1], args[2])
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88 raise Exception()
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89
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90 class OpRegRegReg(ArmInstruction):
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91 """ add rd, rn, rm """
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92 def __init__(self, rd, rn, rm, shift=0):
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93 super().__init__()
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94 self.rd = rd
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95 self.rn = rn
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96 self.rm = rm
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97
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98 def encode(self):
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99 self.token[0:4] = self.rm.num
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100 self.token[4] = 0
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101 self.token[5:7] = 0
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102 self.token[7:12] = 0 # Shift
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103 self.token.Rd = self.rd.num
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104 self.token.Rn = self.rn.num
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105 self.token.S = 0 # Set flags
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106 self.token[21:28] = self.opcode
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107 self.token.cond = 0xE # Always!
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108 return self.token.encode()
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109
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110 def __repr__(self):
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111 return 'add {}, {}, {}'.format(self.rd, self.rn, self.rm)
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112
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113
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114 class Add1(OpRegRegReg):
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115 opcode = 0b0000100
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116
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117
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118 class Sub1(OpRegRegReg):
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119 opcode = 0b0000010
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120
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121
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122 class Orr1(OpRegRegReg):
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123 opcode = 0b0001100
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124
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125
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126 class OpRegRegImm(ArmInstruction):
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127 """ add rd, rn, imm12 """
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128 def __init__(self, rd, rn, imm):
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129 super().__init__()
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130 self.rd = rd
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131 self.rn = rn
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132 self.imm2 = encode_imm32(imm)
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133 self.imm = imm
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134
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135 def encode(self):
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136 self.token[0:12] = self.imm2
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137 self.token.Rd = self.rd.num
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138 self.token.Rn = self.rn.num
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139 self.token.S = 0 # Set flags
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140 self.token[21:28] = self.opcode
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141 self.token.cond = 0xE # Always!
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142 return self.token.encode()
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143
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144 def __repr__(self):
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145 return 'add {}, {}, {}'.format(self.rd, self.rn, self.imm)
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146
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147
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148 class Add2(OpRegRegImm):
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149 opcode = 0b0010100
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150
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151
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152 class Sub2(OpRegRegImm):
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153 opcode = 0b0010010
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154
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155
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156
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157 # Branches:
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158
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159 class BranchBaseRoot(ArmInstruction):
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160 def __init__(self, target):
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161 super().__init__()
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162 self.target = target
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163
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164 def encode(self):
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165 self.token.cond = self.cond
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166 self.token[24:28] = self.opcode
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167 return self.token.encode()
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168
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169 def relocations(self):
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170 return [(self.target, 'b_imm24')]
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171
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172
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173 class BranchBase(BranchBaseRoot):
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174 opcode = 0b1010
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175
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176 class BranchLinkBase(BranchBaseRoot):
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177 opcode = 0b1011
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178
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179 class Bl(BranchLinkBase):
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180 cond = 0xE
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181
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182 class B(BranchBase):
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183 cond = 0xE
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184
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185 class Beq(BranchBase):
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186 cond = 0x0
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187
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188 class Bgt(BranchBase):
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189 cond = 0xC
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190
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191 class Ble(BranchBase):
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192 cond = 0xD
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193
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194
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