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322
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1
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342
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2 from ppci.target.thumb.instructions import Orr, Lsl, Str2, Ldr2, Ldr3
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3 from ppci.target.thumb.instructions import B, Bl, Bgt, Blt, Beq, Bne
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4 from ppci.target.thumb.instructions import Mov2, Mov3, Sub3
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5 from ppci.target.thumb.instructions import Add3, Sub, Cmp, Sub2, Add2, Mul
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322
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6
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7 %%
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8
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323
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9 %terminal ADDI32 SUBI32 MULI32
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10 %terminal ORI32 SHLI32
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322
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11 %terminal CONSTI32 MEMI32 REGI32 CALL
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323
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12 %terminal MOVI32
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322
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13
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14 %%
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15
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323
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16
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357
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17 reg: ADDI32(reg, reg) 2 'd = self.newTmp(); self.emit(Add3, dst=[d], src=[c0, c1]); return d'
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18 reg: SUBI32(reg, reg) 2 'd = self.newTmp(); self.emit(Sub3, dst=[d], src=[c0, c1]); return d'
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19 reg: ORI32(reg, reg) 2 'd = self.newTmp(); self.selector.move(d, c0); self.emit(Orr, dst=[], src=[d, c1]); return d'
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20 reg: SHLI32(reg, reg) 2 'd = self.newTmp(); self.selector.move(d, c0); self.emit(Lsl, dst=[], src=[d, c1]); return d'
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21 reg: MULI32(reg, reg) 2 'd = self.newTmp(); self.selector.move(d, c0); self.emit(Mul, dst=[d], src=[c1, d]); return d'
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322
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22
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357
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23 reg: CONSTI32 3 'd = self.newTmp(); ln = self.selector.frame.addConstant(tree.value); self.emit(Ldr3, dst=[d], others=[ln]); return d'
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24 reg: MEMI32(reg) 4 'd = self.newTmp(); self.emit(Ldr2, dst=[d], src=[c0], others=[0]); return d'
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25 reg: REGI32 1 'return tree.value'
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26 reg: CALL 1 'return self.selector.munchCall(tree.value)'
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322
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27
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28
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357
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29 stmt: MOVI32(MEMI32(addr), reg) 3 'self.emit(Str2, src=[c0, c1])'
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323
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30
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357
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31 addr: reg 0 ''
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