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205
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1 import struct, types
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206
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2 from target import Register, Instruction, Target, Imm8, Label, Imm3
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3 from asmnodes import ASymbol, ANumber, AUnop, ABinop
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202
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4 from ppci import CompilerError
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5 import ir
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6
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7 def u16(h):
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8 return struct.pack('<H', h)
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9
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205
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10 def u32(x):
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11 return struct.pack('<I', x)
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12
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202
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13 armtarget = Target('arm')
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14
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15 class ArmReg(Register):
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16 def __init__(self, num, name):
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17 super().__init__(name)
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18 self.num = num
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19 def __repr__(self):
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20 return self.name
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202
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21
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203
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22 class RegOp:
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23 def __init__(self, num):
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206
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24 assert num < 16
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203
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25 self.num = num
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26
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27 @classmethod
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28 def Create(cls, vop):
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29 if type(vop) is ASymbol:
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30 name = vop.name
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31 regs = {}
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32 for r in armtarget.registers:
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33 regs[r.name] = r
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34 if name in regs:
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35 r = regs[name]
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36 return cls(r.num)
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37
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206
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38 def getRegNum(n):
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39 for r in armtarget.registers:
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40 if r.num == n:
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41 return r
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42
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43 def getRegisterRange(n1, n2):
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44 regs = []
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45 if n1.num < n2.num:
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46 for n in range(n1.num, n2.num + 1):
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47 r = getRegNum(n)
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48 assert r
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49 regs.append(r)
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50 return regs
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203
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51
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205
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52 class RegisterSet:
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53 def __init__(self, regs):
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206
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54 assert type(regs) is set
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55 self.regs = regs
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56 def __repr__(self):
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57 return ','.join([str(r) for r in self.regs])
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58 @classmethod
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59 def Create(cls, vop):
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60 assert type(vop) is AUnop and vop.operation == '{}'
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61 assert type(vop.arg) is list
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62 regs = set()
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63 for arg in vop.arg:
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64 if type(arg) is ASymbol:
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65 reg = RegOp.Create(arg)
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66 if not reg:
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67 return
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68 regs.add(reg)
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69 elif type(arg) is ABinop and arg.op == '-':
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70 reg1 = RegOp.Create(arg.arg1)
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71 reg2 = RegOp.Create(arg.arg2)
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72 if not reg1:
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73 return
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74 if not reg2:
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75 return
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76 for r in getRegisterRange(reg1, reg2):
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77 regs.add(r)
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78 else:
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79 raise Exception('Cannot be')
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80 return cls(regs)
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81
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82 def registerNumbers(self):
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83 return [r.num for r in self.regs]
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84
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85 # 8 bit registers:
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86 r0 = ArmReg(0, 'r0')
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87 armtarget.registers.append(r0)
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88 r1 = ArmReg(1, 'r1')
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89 armtarget.registers.append(r1)
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90 r2 = ArmReg(2, 'r2')
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91 armtarget.registers.append(r2)
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92 r3 = ArmReg(3, 'r3')
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93 armtarget.registers.append(r3)
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94 r4 = ArmReg(4, 'r4')
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95 armtarget.registers.append(r4)
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96 r5 = ArmReg(5, 'r5')
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97 armtarget.registers.append(r5)
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98 r6 = ArmReg(6, 'r6')
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99 armtarget.registers.append(r6)
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100 r7 = ArmReg(7, 'r7')
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101 armtarget.registers.append(r7)
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102 # Other registers:
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103 # TODO
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104 sp = ArmReg(13, 'sp')
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105 armtarget.registers.append(sp)
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106 lr = ArmReg(14, 'lr')
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107 armtarget.registers.append(lr)
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108 pc = ArmReg(15, 'pc')
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109 armtarget.registers.append(pc)
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110
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111 class ArmInstruction(Instruction):
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112 pass
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113
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114 class ldr_ins(ArmInstruction):
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115 mnemonic = 'ldr'
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116 opcode = 1337
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117 irpattern = 'todo'
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118
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119 class dcd_ins(ArmInstruction):
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120 mnemonic = 'dcd'
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121 def __init__(self, expr):
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122 self.expr = expr
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123 def encode(self):
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124 return u32(self.expr)
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202
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125
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126 @armtarget.instruction
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127 class mov_ins(ArmInstruction):
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128 """ mov Rd, imm8, move immediate value into register """
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129 mnemonic = 'mov'
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130 opcode = 4 # 00100 Rd(3) imm8
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131 operands = (RegOp, Imm8)
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132 irpattern = ir.ImmLoad
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133 def __init__(self, rd, imm):
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134 self.imm = imm.imm
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135 self.r = rd.num
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136
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137 @classmethod
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138 def FromIr(cls, ir_ins):
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139 pass
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140
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141 def encode(self):
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142 rd = self.r
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143 opcode = self.opcode
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144 imm8 = self.imm
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145 h = (opcode << 11) | (rd << 8) | imm8
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146 return u16(h)
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147
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203
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148 @armtarget.instruction
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149 class movregreg_ins(ArmInstruction):
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150 """ mov Rd, Rm """
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151 mnemonic = 'mov'
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152 opcode = 8 # 01000 Rd(3) imm8
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153 operands = (RegOp, RegOp)
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154 def __init__(self, rd, rm):
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155 self.rd = rd
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156 self.rm = rm
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157 def encode(self):
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158 rd = self.rd.num
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159 D = (rd & 0x8) >> 3
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160 assert D < 2
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161 rd = rd & 0x7
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162 rm = self.rm.num
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163 assert rm < 16
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164 opcode = self.opcode
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165 h = (opcode << 11) | (3 << 9) | (D << 7) | (rm << 3) | rd
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166 return u16(h)
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167
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168 @armtarget.instruction
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169 class addregregimm3_ins(ArmInstruction):
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170 """ add Rd, Rn, imm3 """
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171 mnemonic = 'add'
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172 opcode = 3 # 00011
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173 operands = (RegOp, RegOp, Imm3)
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174 irpattern = 3
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175 def __init__(self, rd, rn, imm3):
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176 self.rd = rd
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177 self.rn = rn
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178 self.imm3 = imm3
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179 def encode(self):
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180 rd = self.rd.num
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181 rn = self.rn.num
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182 imm3 = self.imm3.imm
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183 opcode = self.opcode
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184 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
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185 return u16(h)
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186
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187 @armtarget.instruction
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188 class cmpregimm8_ins(ArmInstruction):
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189 """ cmp Rn, imm8 """
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190 mnemonic = 'cmp'
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191 opcode = 5 # 00101
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192 operands = (RegOp, Imm8)
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193 def __init__(self, rn, imm):
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194 self.rn = rn
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195 self.imm = imm
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196 def encode(self):
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197 rn = self.rn.num
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198 imm = self.imm.imm
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199 opcode = self.opcode
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200 h = (opcode << 11) | (rn << 8) | imm
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201 return u16(h)
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202
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202
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203 @armtarget.instruction
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205
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204 class jmp_ins(ArmInstruction):
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205 operands = (Label,)
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206 mnemonic = 'jmp'
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207 def __init__(self, target_label):
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208 self.target = target_label
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209 def fixUp(self):
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210 pass
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211 def encode(self):
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212 h = 1337 # TODO
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213 return u16(h)
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214
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215 @armtarget.instruction
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216 class push_ins(ArmInstruction):
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217 operands = (RegisterSet,)
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218 mnemonic = 'push'
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219 def __init__(self, regs):
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220 print(self.operands)
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221 assert (type(regs),) == self.operands, (type(regs),)
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222 self.regs = regs
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223 def __repr__(self):
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224 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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225 def encode(self):
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226 reg_list = 0
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227 M = 0
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228 for n in self.regs.registerNumbers():
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229 if n < 8:
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230 reg_list |= (1 << n)
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231 elif n == 14:
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232 M = 1
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233 else:
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234 raise NotImplementedError('not implemented for this register')
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235 h = (0x5a << 9) | (M << 8) | reg_list
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236 return u16(h)
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237
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238 @armtarget.instruction
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239 class pop_ins(ArmInstruction):
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240 operands = (RegisterSet,)
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241 mnemonic = 'pop'
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242 def __init__(self, regs):
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243 self.regs = regs
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244 def encode(self):
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245 reg_list = 0
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246 P = 0
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247 for n in self.regs.registerNumbers():
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248 if n < 8:
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249 reg_list |= (1 << n)
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250 elif n == 15:
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251 P = 1
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252 else:
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253 raise NotImplementedError('not implemented for this register')
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254 h = (0x5E << 9) | (P << 8) | reg_list
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255 return u16(h)
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256 return u16(0)
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257
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258 @armtarget.instruction
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259 class yield_ins(ArmInstruction):
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260 operands = ()
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261 mnemonic = 'yield'
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262 def encode(self):
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263 return u16(0xbf10)
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264
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265 armtarget.check()
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266
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