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annotate test/sample4.brg @ 327:61c9df5bffce

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Changed emulated board to cortex a8 board
author Windel Bouwman
date Sat, 01 Feb 2014 17:21:21 +0100
parents 44f336460c2a
children 818be710e13d
rev   line source
322
44f336460c2a Half of use of burg spec for arm
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44f336460c2a Half of use of burg spec for arm
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2 %%
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e84047f29c78 Add burg and yacc initial attempts
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8d07a4254f04 Work on burg
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4 %terminal ADDI ADDRLP ASGNI
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5 %terminal CNSTI CVCI IOI INDIRC
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e84047f29c78 Add burg and yacc initial attempts
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7 %%
8d07a4254f04 Work on burg
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8c569fbe60e4 Load yacc and burg dynamic
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9 stmt: ASGNI(disp, reg) 1 (. self.tr(1) .)
8c569fbe60e4 Load yacc and burg dynamic
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10 stmt: reg 0 (. self.tr(2).)
8c569fbe60e4 Load yacc and burg dynamic
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11 reg: ADDI(reg, rc) 1 (. self.tr(3) .)
8c569fbe60e4 Load yacc and burg dynamic
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12 reg: CVCI(INDIRC(disp)) 1 (. self.tr(4) .)
8c569fbe60e4 Load yacc and burg dynamic
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13 reg: IOI 0 (. self.tr(5).)
8c569fbe60e4 Load yacc and burg dynamic
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14 reg: disp 1 (. self.tr(6).)
8c569fbe60e4 Load yacc and burg dynamic
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15 disp: ADDI(reg, con) 1 (. self.tr(7).)
8c569fbe60e4 Load yacc and burg dynamic
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16 disp: ADDRLP 0 (. self.tr(8).)
8c569fbe60e4 Load yacc and burg dynamic
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17 rc: con 0 (. self.tr(9).)
8c569fbe60e4 Load yacc and burg dynamic
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18 rc: reg 0 (. self.tr(10).)
8c569fbe60e4 Load yacc and burg dynamic
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19 con: CNSTI 0 (. self.tr(11).)
8c569fbe60e4 Load yacc and burg dynamic
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20 con: IOI 0 (. self.tr(12).)
318
e84047f29c78 Add burg and yacc initial attempts
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e84047f29c78 Add burg and yacc initial attempts
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