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1 import ir
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2 from irmach import AbstractInstruction as makeIns
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3 from .basetarget import Label, Comment, Alignment, LabelRef, DebugInfo, Nop
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4 from .instructionselector import InstructionSelector
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5 from .arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3, B, Bl, Bgt, Blt, Beq
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6 from .arminstructions import Mov2, Mov3
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7 from .arminstructions import Add, Sub, Cmp
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8 from .basetarget import Imm8, Imm7, Imm3
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9
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10
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11 class ArmInstructionSelector(InstructionSelector):
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12 """ Instruction selector for the arm architecture """
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13 def munchExpr(self, e):
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14 if isinstance(e, ir.Alloc):
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15 return 0
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16 elif isinstance(e, ir.Binop) and e.operation == '+' and \
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17 isinstance(e.b, ir.Const) and e.b.value < 8:
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18 a = self.munchExpr(e.a)
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19 d = self.newTmp()
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20 c = Imm3(e.b.value)
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21 self.emit(arm.addregregimm3_ins, others=[c], dst=[d], src=[a])
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22 return d
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23 elif isinstance(e, ir.Binop) and e.operation == '+':
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24 a = self.munchExpr(e.a)
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25 b = self.munchExpr(e.b)
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26 d = self.newTmp()
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27 self.emit(Add, dst=[d], src=[a, b])
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28 return d
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29 elif isinstance(e, ir.Binop) and e.operation == '-' and \
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30 isinstance(e.b, ir.Const) and e.b.value < 8:
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31 a = self.munchExpr(e.a)
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32 d = self.newTmp()
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33 c = Imm3(e.b.value)
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34 self.emit(arm.subregregimm3_ins, others=[c], dst=[d], src=[a])
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35 return d
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36 elif isinstance(e, ir.Binop) and e.operation == '-':
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37 a = self.munchExpr(e.a)
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38 b = self.munchExpr(e.b)
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39 d = self.newTmp()
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40 self.emit(Sub, dst=[d], src=[a, b])
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41 return d
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42 elif isinstance(e, ir.Binop) and e.operation == '|':
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43 a = self.munchExpr(e.a)
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44 b = self.munchExpr(e.b)
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45 d = self.newTmp()
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46 self.move(d, a)
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47 self.emit(Orr, dst=[], src=[b, d])
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48 return d
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49 elif isinstance(e, ir.Binop) and e.operation == '<<':
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50 a = self.munchExpr(e.a)
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51 b = self.munchExpr(e.b)
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52 d = self.newTmp()
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53 self.move(d, a)
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54 self.emit(Lsl, dst=[], src=[b, d]) # TODO: is d a source variable?
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55 return d
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56 elif isinstance(e, ir.Binop) and e.operation == '*':
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57 a = self.munchExpr(e.a)
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58 b = self.munchExpr(e.b)
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59 d = self.newTmp()
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60 self.move(d, a)
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61 # this mul instruction has operands swapped:
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62 self.emit(arm.mulregreg_ins, dst=[d], src=[b, d])
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63 return d
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64 elif isinstance(e, ir.Const) and e.value < 256:
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65 d = self.newTmp()
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66 self.emit(Mov3, others=[Imm8(e.value)], dst=[d])
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67 return d
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68 elif isinstance(e, ir.Const) and e.value < (2**31):
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69 d = self.newTmp()
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70 ln = LabelRef(self.frame.addConstant(e.value))
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71 self.emit(Ldr3, others=[ln], dst=[d])
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72 return d
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73 elif isinstance(e, ir.Mem) and isinstance(e.e, ir.Binop) and \
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74 e.e.operation == '+' and isinstance(e.e.b, ir.Const):
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75 base = self.munchExpr(e.e.a)
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76 d = self.newTmp()
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77 c = e.e.b.value
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78 self.emit(Ldr2, others=[c], src=[base], dst=[d])
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79 return d
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80 elif isinstance(e, ir.Mem):
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81 # Load from memory
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82 base = self.munchExpr(e.e)
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83 d = self.newTmp()
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84 self.emit(Ldr2, others=[0], src=[base], dst=[d])
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85 return d
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86 elif isinstance(e, ir.Temp):
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87 return e
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88 elif isinstance(e, ir.Call):
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89 # Move arguments into proper locations:
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90 reguses = []
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91 for i, a in enumerate(e.arguments):
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92 loc = self.frame.argLoc(i)
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93 m = ir.Move(loc, a)
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94 self.munchStm(m)
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95 if isinstance(loc, ir.Temp):
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96 reguses.append(loc)
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97 self.emit(Bl(LabelRef(e.f.name)), src=reguses, dst=[self.frame.rv])
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98 d = self.newTmp()
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99 self.move(d, self.frame.rv)
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100 return d
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101 else:
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102 raise NotImplementedError('Expr --> {}'.format(e))
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103
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104 def munchStm(self, s):
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105 if isinstance(s, ir.Terminator):
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106 pass
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107 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem) and \
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108 isinstance(s.dst.e, ir.Binop) and s.dst.e.operation == '+' and \
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109 isinstance(s.dst.e.b, ir.Const):
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110 a = self.munchExpr(s.dst.e.a)
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111 val = self.munchExpr(s.src)
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112 c = s.dst.e.b.value
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113 self.emit(Str2, others=[c], src=[a, val])
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114 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Mem):
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115 memloc = self.munchExpr(s.dst.e)
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116 val = self.munchExpr(s.src)
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117 self.emit(Str2, others=[0], src=[memloc, val])
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118 elif isinstance(s, ir.Move) and isinstance(s.dst, ir.Temp):
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119 val = self.munchExpr(s.src)
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120 dreg = s.dst
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121 self.move(dreg, val)
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122 elif isinstance(s, ir.Exp):
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123 # Generate expression code and discard the result.
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124 x = self.munchExpr(s.e)
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125 self.emit(Nop(), src=[x])
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126 elif isinstance(s, ir.Jump):
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127 tgt = self.targets[s.target]
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128 self.emit(B(LabelRef(s.target.name)), jumps=[tgt])
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129 elif isinstance(s, ir.CJump):
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130 a = self.munchExpr(s.a)
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131 b = self.munchExpr(s.b)
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132 self.emit(Cmp, src=[a, b])
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133 ntgt = self.targets[s.lab_no]
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134 ytgt = self.targets[s.lab_yes]
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135 jmp_ins = makeIns(B(LabelRef(s.lab_no.name)), jumps=[ntgt])
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136 opnames = {'<': Blt, '>':Bgt, '==':Beq}
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137 op = opnames[s.cond](LabelRef(s.lab_yes.name))
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138 self.emit(op, jumps=[ytgt, jmp_ins]) # Explicitely add fallthrough
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139 self.emit2(jmp_ins)
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140 else:
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141 raise NotImplementedError('Stmt --> {}'.format(s))
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142
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143 def move(self, dst, src):
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144 self.emit(Mov2, src=[src], dst=[dst])
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