annotate python/testregalloc.py @ 281:4496cae24d7f

Improved logview
author Windel Bouwman
date Sat, 02 Nov 2013 11:11:40 +0100
parents 02385f62f250
children
rev   line source
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1 import unittest
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2 import os
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3 import sys
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4 from irmach import AbstractInstruction as makeIns, Frame
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5 import registerallocator
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6 import ir
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7 from target import Nop
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9
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10 class RegAllocTestCase(unittest.TestCase):
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11 def setUp(self):
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12 self.ra = registerallocator.RegisterAllocator()
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13
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14 def testRegAlloc(self):
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15 f = Frame('tst')
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16 f.regs = [1,2,3,4,5,6] # for test use numbers!
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17 f.tempMap = {}
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18 t1 = ir.Temp('t1')
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19 t2 = ir.Temp('t2')
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20 t3 = ir.Temp('t3')
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21 t4 = ir.Temp('t4')
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22 t5 = ir.Temp('t5')
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23 f.instructions.append(makeIns(Nop, dst=[t1]))
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24 f.instructions.append(makeIns(Nop, dst=[t2]))
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25 f.instructions.append(makeIns(Nop, dst=[t3]))
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26 f.instructions.append(makeIns(Nop, dst=[t4], src=[t1, t2]))
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27 f.instructions.append(makeIns(Nop, dst=[t5], src=[t4, t3]))
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28 f.instructions.append(makeIns(Nop, src=[t5]))
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29 self.ra.allocFrame(f)
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30 self.conflict(t1, t2)
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31 self.conflict(t2, t3)
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32
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33 def conflict(self, ta, tb):
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34 self.assertNotEqual(self.ra.Node(ta).color, self.ra.Node(tb).color)
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36 def testRegCoalesc(self):
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37 f = Frame('tst')
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38 f.regs = [1,2,3,4,5,6] # for test use numbers!
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39 f.tempMap = {}
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40 t1 = ir.Temp('t1')
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41 t2 = ir.Temp('t2')
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42 t3 = ir.Temp('t3')
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43 t4 = ir.Temp('t4')
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44 t5 = ir.Temp('t5')
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45 t6 = ir.Temp('t6')
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46 f.instructions.append(makeIns(Nop, dst=[t1]))
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47 f.instructions.append(makeIns(Nop, dst=[t2]))
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48 f.instructions.append(makeIns(Nop, dst=[t3]))
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49 f.instructions.append(makeIns(Nop, dst=[t4], src=[t2, t1]))
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50 f.instructions.append(makeIns(Nop, dst=[t5], src=[t3]))
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51 f.instructions.append(makeIns(Nop, dst=[t5], src=[t4, t5]))
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52 f.instructions.append(makeIns(Nop, dst=[t6], src=[t5]))
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53 f.instructions.append(makeIns(Nop, src=[t6]))
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54 self.ra.allocFrame(f)
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55 self.conflict(t1, t2)
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56 self.conflict(t2, t3)
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57 self.conflict(t1, t3)
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58
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59 if __name__ == '__main__':
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60 unittest.main()
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