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1
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2 from ..basetarget import Instruction
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346
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3 from ...bitfun import rotate_left
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342
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4
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5 from .token import ArmToken
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345
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6 from .registers import R0, SP, ArmRegister
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7
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8
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9 def encode_imm32(v):
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10 """ Bundle 32 bit value into 4 bits rotation and 8 bits value
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11 """
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12 for i in range(0, 16):
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13 v2 = rotate_left(v, i*2)
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14 if (v2 & 0xFFFFFF00) == 0:
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15 rotation = i
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16 val = v2 & 0xFF
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17 x = (rotation << 8) | val
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18 return x
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19 raise Exception("Invalid value {}".format(v))
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342
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20
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21 # Instructions:
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22
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23 class ArmInstruction(Instruction):
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24 def __init__(self):
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25 self.token = ArmToken()
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26
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27
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346
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28 class Dcd(ArmInstruction):
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29 def __init__(self, v):
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30 super().__init__()
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31 self.v = v
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32
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33 def encode(self):
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34 self.token[0:32] = self.v
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35 return self.token.encode()
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36
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37
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38 def Mov(*args):
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39 if len(args) == 2:
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40 if isinstance(args[1], int):
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41 return Mov1(*args)
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42 elif isinstance(args[1], ArmRegister):
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43 return Mov2(*args)
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44 raise Exception()
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45
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46
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47 class Mov1(ArmInstruction):
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342
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48 """ Mov Rd, imm16 """
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49 def __init__(self, reg, imm):
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50 super().__init__()
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346
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51 assert type(imm) is int
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342
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52 self.reg = reg
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53 self.imm = imm
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54
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55 def encode(self):
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346
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56 self.token[0:12] = encode_imm32(self.imm)
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345
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57 self.token.Rd = self.reg.num
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342
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58 self.token[16:20] = 0
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346
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59 self.token[20] = 0 # Set flags
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342
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60 self.token[21:28] = 0b0011101
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346
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61 self.token.cond = AL
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342
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62 return self.token.encode()
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63
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64 def relocations(self):
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65 return []
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66
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67 def __repr__(self):
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345
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68 return 'Mov {}, {}'.format(self.reg, self.imm)
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69
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70
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346
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71 class Mov2(ArmInstruction):
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72 def __init__(self, rd, rm):
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73 super().__init__()
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74 self.rd = rd
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75 self.rm = rm
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76
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77 def encode(self):
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78 self.token[0:4] = self.rm.num
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79 self.token[4:12] = 0
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80 self.token[12:16] = self.rd.num
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81 self.token[16:20] = 0
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82 self.token.S = 0
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83 self.token[21:28] = 0xD
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84 self.token.cond = AL
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85 return self.token.encode()
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86
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87
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345
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88 def Add(*args):
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89 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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90 isinstance(args[1], ArmRegister):
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91 if isinstance(args[2], ArmRegister):
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92 return Add1(args[0], args[1], args[2])
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93 elif isinstance(args[2], int):
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94 return Add2(args[0], args[1], args[2])
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95 raise Exception()
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96
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97 def Sub(*args):
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98 if len(args) == 3 and isinstance(args[0], ArmRegister) and \
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99 isinstance(args[1], ArmRegister):
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100 if isinstance(args[2], ArmRegister):
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101 return Sub1(args[0], args[1], args[2])
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102 elif isinstance(args[2], int):
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103 return Sub2(args[0], args[1], args[2])
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104 raise Exception()
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105
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346
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106 def Mul(*args):
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107 return Mul1(args[0], args[1], args[2])
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108
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109
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110 class Mul(ArmInstruction):
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111 def __init__(self, rd, rn, rm):
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112 super().__init__()
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113 self.rd = rd
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114 self.rn = rn
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115 self.rm = rm
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116
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117 def encode(self):
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118 self.token[0:4] = self.rn.num
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119 self.token[4:8] = 0b1001
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120 self.token[8:12] = self.rm.num
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121 self.token[16:20] = self.rd.num
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122 self.token.S = 0
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123 self.token.cond = AL
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124 return self.token.encode()
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125
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126
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345
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127 class OpRegRegReg(ArmInstruction):
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128 """ add rd, rn, rm """
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129 def __init__(self, rd, rn, rm, shift=0):
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130 super().__init__()
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131 self.rd = rd
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132 self.rn = rn
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133 self.rm = rm
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134
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135 def encode(self):
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136 self.token[0:4] = self.rm.num
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137 self.token[4] = 0
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138 self.token[5:7] = 0
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139 self.token[7:12] = 0 # Shift
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140 self.token.Rd = self.rd.num
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141 self.token.Rn = self.rn.num
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142 self.token.S = 0 # Set flags
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143 self.token[21:28] = self.opcode
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144 self.token.cond = 0xE # Always!
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145 return self.token.encode()
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146
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147 def __repr__(self):
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148 return 'add {}, {}, {}'.format(self.rd, self.rn, self.rm)
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149
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150
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151 class Add1(OpRegRegReg):
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152 opcode = 0b0000100
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153
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154
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155 class Sub1(OpRegRegReg):
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156 opcode = 0b0000010
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157
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158
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159 class Orr1(OpRegRegReg):
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160 opcode = 0b0001100
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161
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342
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162
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345
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163 class OpRegRegImm(ArmInstruction):
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164 """ add rd, rn, imm12 """
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165 def __init__(self, rd, rn, imm):
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166 super().__init__()
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167 self.rd = rd
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168 self.rn = rn
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169 self.imm2 = encode_imm32(imm)
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170 self.imm = imm
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171
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172 def encode(self):
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173 self.token[0:12] = self.imm2
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174 self.token.Rd = self.rd.num
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175 self.token.Rn = self.rn.num
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176 self.token.S = 0 # Set flags
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177 self.token[21:28] = self.opcode
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178 self.token.cond = 0xE # Always!
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179 return self.token.encode()
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180
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181 def __repr__(self):
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182 return 'add {}, {}, {}'.format(self.rd, self.rn, self.imm)
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183
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184
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185 class Add2(OpRegRegImm):
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186 opcode = 0b0010100
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187
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188
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189 class Sub2(OpRegRegImm):
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190 opcode = 0b0010010
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191
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192
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193
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194 # Branches:
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195
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196 class BranchBaseRoot(ArmInstruction):
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197 def __init__(self, target):
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198 super().__init__()
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199 self.target = target
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200
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201 def encode(self):
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202 self.token.cond = self.cond
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203 self.token[24:28] = self.opcode
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204 return self.token.encode()
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205
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206 def relocations(self):
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207 return [(self.target, 'b_imm24')]
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208
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209
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210 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = range(15)
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211
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345
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212 class BranchBase(BranchBaseRoot):
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213 opcode = 0b1010
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214
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215 class BranchLinkBase(BranchBaseRoot):
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216 opcode = 0b1011
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217
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218 class Bl(BranchLinkBase):
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219 cond = AL
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220
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221 class B(BranchBase):
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222 cond = AL
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223
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224 class Beq(BranchBase):
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225 cond = EQ
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226
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227 class Bgt(BranchBase):
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228 cond = GT
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229
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230 class Ble(BranchBase):
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231 cond = LE
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232
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233 class Blt(BranchBase):
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234 cond = LT
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235
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236
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237 # Memory:
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238
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239 def reg_list_to_mask(reg_list):
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240 mask = 0
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241 for reg in reg_list:
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242 mask |= (1 << reg.num)
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243 return mask
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244
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245
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246 class Push(ArmInstruction):
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247 def __init__(self, register_set):
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248 super().__init__()
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249 self.reg_list = register_set
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250
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251 def encode(self):
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252 self.token.cond = AL
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253 self.token[16:28] = 0b100100101101
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254 reg_list = 0
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255 self.token[0:16] = reg_list_to_mask(self.reg_list)
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256 return self.token.encode()
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257
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258 class Pop(ArmInstruction):
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259 def __init__(self, register_set):
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260 super().__init__()
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261 self.reg_list = register_set
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262
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263 def encode(self):
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264 self.token.cond = AL
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265 self.token[16:28] = 0b100010111101
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266 self.token[0:16] = reg_list_to_mask(self.reg_list)
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267 return self.token.encode()
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268
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269
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346
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270 def Ldr(*args):
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271 if len(args) == 3 and isinstance(args[1], ArmRegister):
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272 return Ldr1(*args)
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273 elif len(args) == 2 and isinstance(args[1], ArmRegister):
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274 return Ldr1(args[0], args[1], 0)
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275 raise Exception()
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276
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277 def Str(*args):
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278 if len(args) == 3 and isinstance(args[1], ArmRegister):
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279 return Str1(*args)
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280 elif len(args) == 2 and isinstance(args[1], ArmRegister):
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281 return Str1(args[0], args[1], 0)
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282 raise Exception()
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283
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284
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285 class LdrStrBase(ArmInstruction):
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286 def __init__(self, rt, rn, offset):
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287 super().__init__()
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288 self.rt = rt
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289 self.rn = rn
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290 self.offset = offset
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291
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292 def encode(self):
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293 self.token.cond = AL
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294 self.token.Rn = self.rn.num
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295 self.token[25:28] = self.opcode
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296 self.token[20] = self.bit20
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297 self.token[12:16] = self.rt.num
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298 self.token[24] = 1 # Index
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299 if self.offset >= 0:
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300 self.token[23] = 1 # U == 1 'add'
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301 self.token[0:12] = self.offset
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302 else:
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303 self.token[23] = 0
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304 self.token[0:12] = -self.offset
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305 return self.token.encode()
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306
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307
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308 class Str1(LdrStrBase):
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309 opcode = 0b010
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310 bit20 = 0
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311
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312
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313 class Ldr1(LdrStrBase):
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314 opcode = 0b010
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315 bit20 = 1
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316
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317
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318 class Ldr3(ArmInstruction):
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319 """ Load PC relative constant value """
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320 def __init__(self, rt, label):
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321 self.rt = rt
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322 self.label = label
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323
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