annotate python/ppci/target/arm/armv7.lidl @ 348:442fb043d149

Added log option to zcc
author Windel Bouwman
date Sat, 08 Mar 2014 15:32:33 +0100
parents 86b02c98a717
children
rev   line source
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2 # This file specifies the encoding of the arm instruction set.
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4 fields {
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5 word16 16 {
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6 opcode 15:12
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7 top2 15:14
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8 top6 15:10
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9 data_opcode 9..6
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10 opB 11:9
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11 Rm 8:6
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12 Rn 5:3
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13 Rt 2:0
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14 }
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15 }
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17 patterns {
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18 add = 0
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19 sub, mul = 1..2
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20 [r1, r2, r3, r4, r5] is todo = 1..5
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21 [STR, STRH, STRB, LDRSB, LDR, LDRH, LDRB, LDRSH] is opcode = 0b0101 & opB = {0 to 7}
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22
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23 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = 0..14
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24 [AND, EOR, LSL, LSR, ASR, ADC, SBC, ROR, TST, RSB, CMP, CMN, ORR, MUL, BIC, MVN] is 0..15
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26 memop is STR | STRH | STRB | LDRSB | LDR | LDR | LDRH | LDRB | LDRSH
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27 }
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30 constructors
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31 {
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32 alu rs1, reg_or_imm, rd
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33 memop Rt, [Rn, Rm] is memop & Rt & Rn & Rm
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34 }
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