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1 import unittest
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342
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2 from ppci.outstream import BinaryOutputStream
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335
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3 from ppci.objectfile import ObjectFile
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292
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4 from testasm import AsmTestCaseBase
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345
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5 from ppci.target.target_list import arm_target
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6
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7
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8 class ArmAssemblerTestCase(AsmTestCaseBase):
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340
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9 """ ARM-mode (not thumb-mode) instruction assembly test case """
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10 def setUp(self):
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11 self.t = arm_target
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12 self.obj = ObjectFile()
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13 self.ostream = BinaryOutputStream(self.obj)
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14 self.ostream.select_section('.text')
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381
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15 self.assembler = arm_target.assembler
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340
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16
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17 def testMovImm(self):
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18 self.feed('mov r4, 100')
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19 self.check('6440a0e3')
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20
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21 def testMovImm2(self):
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22 self.feed('mov sp, 0x6000')
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23 self.check('06daa0e3')
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24
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362
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25 def testMovReg(self):
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26 self.feed('mov r3, sp')
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27 self.feed('mov pc, lr')
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28 self.feed('mov pc, r2')
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29 self.feed('mov sp, r4')
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30 self.feed('mov r5, r6')
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31 self.check('0d30a0e1 0ef0a0e1 02f0a0e1 04d0a0e1 0650a0e1')
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32
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33 def testAdd2(self):
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34 self.feed('add r12, r11, 300')
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35 self.check('4bcf8be2')
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36
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37 def testAdd1(self):
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38 self.feed('add r9, r7, r2')
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39 self.check('029087e0')
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40
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41 def testSub1(self):
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42 self.feed('sub r5, r6, r2')
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43 self.check('025046e0')
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44
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45 def testSub2(self):
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46 self.feed('sub r0, r1, 0x80000001')
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47 self.check('060141e2')
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48
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356
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49 def testAnd1(self):
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50 self.feed('and r9, r0, r2')
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51 self.feed('and r4, r8, r6')
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52 self.check('029000e0 064008e0')
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53
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54 def testOrr1(self):
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55 self.feed('orr r8, r7, r6')
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56 self.check('068087e1')
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57
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356
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58 def testLsl(self):
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59 self.feed('lsl r11, r5, r3')
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60 self.feed('lsl r4, r8, r6')
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61 self.check('15b3a0e1 1846a0e1')
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62
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63 def testLsr(self):
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64 self.feed('lsr r9, r0, r2')
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65 self.feed('lsr r4, r8, r6')
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66 self.check('3092a0e1 3846a0e1')
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67
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68 def testBranches(self):
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69 self.feed("""b sjakie
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70 ble sjakie
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71 bgt sjakie
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72 beq sjakie
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73 bl sjakie
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74 sjakie:
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75 b sjakie
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76 ble sjakie
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77 bgt sjakie
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78 beq sjakie
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79 bl sjakie""")
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80 self.check('030000ea 020000da 010000ca 0000000a ffffffeb feffffea fdffffda fcffffca fbffff0a faffffeb')
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81
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82 def testPush(self):
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83 self.feed('push {r11,r5,r4,lr}')
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84 self.check('30482de9')
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85
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86 def testPop(self):
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87 self.feed('pop {r4,r5,r6}')
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88 self.check('7000bde8')
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89
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90 def testStr(self):
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91 self.feed('str r9, [r2, 33]')
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92 self.check('219082e5')
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93
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94 def testLdr(self):
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95 self.feed('ldr r5, [r3, 87]')
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96 self.check('575093e5')
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97
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98 def testLdrLabel(self):
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99 self.feed('ldr r5, lab1')
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100 self.feed('ldr r11, lab1')
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101 self.feed('ldr r10, lab1')
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102 self.feed('lab1:')
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103 self.feed('dcd 0x12345566')
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104 self.check('04509fe5 00b09fe5 04a01fe5 66553412')
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105
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106 def testAdr(self):
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107 self.feed('adr r5, cval')
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108 self.feed('adr r9, cval')
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109 self.feed('adr r8, cval')
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110 self.feed('cval:')
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111 self.feed('adr r11, cval')
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112 self.feed('adr r12, cval')
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113 self.feed('adr r1, cval')
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114 self.check('04508fe2 00908fe2 04804fe2 08b04fe2 0cc04fe2 10104fe2')
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115
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116 def testLdrLabelAddress(self):
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117 self.feed('ldr r8, =a')
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118 self.feed('a:')
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381
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119 self.check('04801fe5 04000000')
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120
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121 def testLdrLabelAddressAt10000(self):
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122 """ Link code at 0x10000 and check if symbol was correctly patched """
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123 self.feed('ldr r8, =a')
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124 self.feed('a:')
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125 self.check('04801fe5 04000100', {'.text':0x10000})
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126
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127 def testCmp(self):
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128 self.feed('cmp r4, r11')
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129 self.feed('cmp r5, 0x50000')
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130 self.check('0b0054e1 050855e3')
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131
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132 def testSequence1(self):
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133 self.feed('sub r4,r5,23')
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134 self.feed('blt x')
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135 self.feed('x:')
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136 self.feed('mul r4,r5,r2')
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137 self.check('174045e2 ffffffba 950204e0')
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138
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362
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139 def testMcr(self):
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140 """ Test move coprocessor register from arm register """
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141 self.feed('mcr p15, 0, r1, c2, c0, 0')
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142 self.feed('mcr p14, 0, r1, c8, c7, 0')
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143 self.check('101f02ee 171e08ee')
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144
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145 def testMrc(self):
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146 self.feed('mrc p15, 0, r1, c2, c0, 0')
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147 self.feed('mrc p14, 0, r1, c8, c7, 0')
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148 self.check('101f12ee 171e18ee')
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149
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150
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151 if __name__ == '__main__':
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152 unittest.main()
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