# HG changeset patch
# User Thinker K.F. Li <thinker@branda.to>
# Date 1235472796 -28800
# Node ID 68ecd42850d3b1015cfac6e1bf01ca512f7cf5fe
# Parent  520f45b72ba79692dd94a314ac65cf62111172d9
Start shifting when TAP transiting from CAP to SHIFT states.
- It assumes last bit is shifted when transiting from SHIFT states to
  EXIT1.

diff -r 520f45b72ba7 -r 68ecd42850d3 py_avrjtag/jtagdev.py
--- a/py_avrjtag/jtagdev.py	Tue Feb 24 14:33:23 2009 +0800
+++ b/py_avrjtag/jtagdev.py	Tue Feb 24 18:53:16 2009 +0800
@@ -85,10 +85,10 @@
             return
         
         if self.state == self.ST_IDLE:
-            ptn, ptn_nbits = tms_ptns.TMS_SHIFT_IR
+            ptn, ptn_nbits = tms_ptns.TMS_CAP_IR
             self._send_tms(ptn, ptn_nbits)
-        elif self.state == self.ST_EXIT1_DR:
-            ptn, ptn_nbits = tms_ptns.TMS_EXIT1_DR_2_SHIFT_IR
+        elif self.state == self.ST_SHIFT__DR:
+            ptn, ptn_nbits = tms_ptns.TMS_SHIFT_DR_2_CAP_IR
             self._send_tms(ptn, ptn_nbits)
         else:
             raise RuntimeError, 'Transite to shift IR state from invalid state'
@@ -100,10 +100,10 @@
             return
         
         if self.state == self.ST_IDLE:
-            ptn, ptn_nbits = tms_ptns.TMS_SHIFT_DR
+            ptn, ptn_nbits = tms_ptns.TMS_CAP_DR
             self._send_tms(ptn, ptn_nbits)
-        elif self.state == self.ST_EXIT1_IR:
-            ptn, ptn_nbits = tms_ptns.TMS_EXIT1_IR_2_SHIFT_DR
+        elif self.state == self.ST_SHIFT_IR:
+            ptn, ptn_nbits = tms_ptns.TMS_SHIFT_IR_2_CAP_DR
             self._send_tms(ptn, ptn_nbits)
         else:
             raise RuntimeError, 'Transite to shift DR state from invalid state'