Mercurial > avr_jtag
diff py_avrjtag/jtagdev.py @ 13:1ea479d26fce tip
Make sure shifting phase and add bypass.py.
- shifting phase is started after entering SHIFT state
Transition from CAP to SHIFT does not induce shifting.
- shifting phase is stoped after leaving SHIFT state.
Transition from SHIFT to EXIT1 also induce a bit of shifting.
| author | Thinker K.F. Li <thinker@branda.to> |
|---|---|
| date | Wed, 25 Feb 2009 20:08:29 +0800 |
| parents | 68ecd42850d3 |
| children |
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--- a/py_avrjtag/jtagdev.py Tue Feb 24 18:53:16 2009 +0800 +++ b/py_avrjtag/jtagdev.py Wed Feb 25 20:08:29 2009 +0800 @@ -3,6 +3,14 @@ debug_frame = 0 +def dump_frame(frame): + r = '' + for c in frame: + r = r + ('%02x ' % (ord(c))) + pass + print r + pass + class jtagdev(object): ST_RESET = 0 ST_IDLE = 1 @@ -13,7 +21,7 @@ def __init__(self, fo): self.fo = fo - self.state = self.ST_IDLE + self.state = self.ST_RESET self.seq = 0 pass @@ -58,7 +66,7 @@ if not frame: return None if debug_frame: - print repr(frame) + dump_frame(frame) pass cmd = cmd_proto.cmd() @@ -85,13 +93,14 @@ return if self.state == self.ST_IDLE: - ptn, ptn_nbits = tms_ptns.TMS_CAP_IR - self._send_tms(ptn, ptn_nbits) - elif self.state == self.ST_SHIFT__DR: - ptn, ptn_nbits = tms_ptns.TMS_SHIFT_DR_2_CAP_IR - self._send_tms(ptn, ptn_nbits) + ptn, ptn_nbits = tms_ptns.TMS_SHIFT_IR + elif self.state == self.ST_EXIT1_DR: + ptn, ptn_nbits = tms_ptns.TMS_EXIT1_DR_2_SHIFT_IR + elif self.state == self.ST_EXIT1_IR: + ptn, ptn_nbits = tms_ptns.TMS_EXIT1_IR_2_SHIFT_IR else: raise RuntimeError, 'Transite to shift IR state from invalid state' + self._send_tms(ptn, ptn_nbits) self.state = self.ST_SHIFT_IR pass @@ -100,14 +109,15 @@ return if self.state == self.ST_IDLE: - ptn, ptn_nbits = tms_ptns.TMS_CAP_DR - self._send_tms(ptn, ptn_nbits) - elif self.state == self.ST_SHIFT_IR: - ptn, ptn_nbits = tms_ptns.TMS_SHIFT_IR_2_CAP_DR - self._send_tms(ptn, ptn_nbits) + ptn, ptn_nbits = tms_ptns.TMS_SHIFT_DR + elif self.state == self.ST_EXIT1_IR: + ptn, ptn_nbits = tms_ptns.TMS_EXIT1_IR_2_SHIFT_DR + elif self.state == self.ST_EXIT1_DR: + ptn, ptn_nbits = tms_ptns.TMS_EXIT1_DR_2_SHIFT_DR else: raise RuntimeError, 'Transite to shift DR state from invalid state' pass + self._send_tms(ptn, ptn_nbits) self.state = self.ST_SHIFT_DR pass @@ -171,15 +181,15 @@ return (ord(data[byte_off]) >> bit_off) & 0x1 def identify_components(dev): - dev.go_shift_IR() - reply = dev.wait_reply() - if reply.code != cmd_proto.CPCMD_ACK: - raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) +# dev.go_shift_IR() +# reply = dev.wait_reply() +# if reply.code != cmd_proto.CPCMD_ACK: +# raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) - dev.shift_IR('\x02', 4) - reply = dev.wait_reply() - if reply.code != cmd_proto.CPCMD_ACK: - raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) +# dev.shift_IR('\x04', 4) +# reply = dev.wait_reply() +# if reply.code != cmd_proto.CPCMD_ACK: +# raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) dev.go_shift_DR() reply = dev.wait_reply()