Mercurial > avr_jtag
comparison py_avrjtag/jtagdev.py @ 13:1ea479d26fce tip
Make sure shifting phase and add bypass.py.
- shifting phase is started after entering SHIFT state
Transition from CAP to SHIFT does not induce shifting.
- shifting phase is stoped after leaving SHIFT state.
Transition from SHIFT to EXIT1 also induce a bit of shifting.
author | Thinker K.F. Li <thinker@branda.to> |
---|---|
date | Wed, 25 Feb 2009 20:08:29 +0800 |
parents | 68ecd42850d3 |
children |
comparison
equal
deleted
inserted
replaced
12:68ecd42850d3 | 13:1ea479d26fce |
---|---|
1 import tms_ptns | 1 import tms_ptns |
2 import cmd_proto | 2 import cmd_proto |
3 | 3 |
4 debug_frame = 0 | 4 debug_frame = 0 |
5 | |
6 def dump_frame(frame): | |
7 r = '' | |
8 for c in frame: | |
9 r = r + ('%02x ' % (ord(c))) | |
10 pass | |
11 print r | |
12 pass | |
5 | 13 |
6 class jtagdev(object): | 14 class jtagdev(object): |
7 ST_RESET = 0 | 15 ST_RESET = 0 |
8 ST_IDLE = 1 | 16 ST_IDLE = 1 |
9 ST_SHIFT_DR = 2 | 17 ST_SHIFT_DR = 2 |
11 ST_EXIT1_DR = 4 | 19 ST_EXIT1_DR = 4 |
12 ST_EXIT1_IR = 5 | 20 ST_EXIT1_IR = 5 |
13 | 21 |
14 def __init__(self, fo): | 22 def __init__(self, fo): |
15 self.fo = fo | 23 self.fo = fo |
16 self.state = self.ST_IDLE | 24 self.state = self.ST_RESET |
17 self.seq = 0 | 25 self.seq = 0 |
18 pass | 26 pass |
19 | 27 |
20 def _send_cmd(self, code, data): | 28 def _send_cmd(self, code, data): |
21 cmd = cmd_proto.cmd(self.seq, code, data) | 29 cmd = cmd_proto.cmd(self.seq, code, data) |
56 pass | 64 pass |
57 | 65 |
58 if not frame: | 66 if not frame: |
59 return None | 67 return None |
60 if debug_frame: | 68 if debug_frame: |
61 print repr(frame) | 69 dump_frame(frame) |
62 pass | 70 pass |
63 | 71 |
64 cmd = cmd_proto.cmd() | 72 cmd = cmd_proto.cmd() |
65 r = cmd.from_frame(frame) | 73 r = cmd.from_frame(frame) |
66 if r: | 74 if r: |
83 def go_shift_IR(self): | 91 def go_shift_IR(self): |
84 if self.state == self.ST_SHIFT_IR: | 92 if self.state == self.ST_SHIFT_IR: |
85 return | 93 return |
86 | 94 |
87 if self.state == self.ST_IDLE: | 95 if self.state == self.ST_IDLE: |
88 ptn, ptn_nbits = tms_ptns.TMS_CAP_IR | 96 ptn, ptn_nbits = tms_ptns.TMS_SHIFT_IR |
89 self._send_tms(ptn, ptn_nbits) | 97 elif self.state == self.ST_EXIT1_DR: |
90 elif self.state == self.ST_SHIFT__DR: | 98 ptn, ptn_nbits = tms_ptns.TMS_EXIT1_DR_2_SHIFT_IR |
91 ptn, ptn_nbits = tms_ptns.TMS_SHIFT_DR_2_CAP_IR | 99 elif self.state == self.ST_EXIT1_IR: |
92 self._send_tms(ptn, ptn_nbits) | 100 ptn, ptn_nbits = tms_ptns.TMS_EXIT1_IR_2_SHIFT_IR |
93 else: | 101 else: |
94 raise RuntimeError, 'Transite to shift IR state from invalid state' | 102 raise RuntimeError, 'Transite to shift IR state from invalid state' |
103 self._send_tms(ptn, ptn_nbits) | |
95 self.state = self.ST_SHIFT_IR | 104 self.state = self.ST_SHIFT_IR |
96 pass | 105 pass |
97 | 106 |
98 def go_shift_DR(self): | 107 def go_shift_DR(self): |
99 if self.state == self.ST_SHIFT_DR: | 108 if self.state == self.ST_SHIFT_DR: |
100 return | 109 return |
101 | 110 |
102 if self.state == self.ST_IDLE: | 111 if self.state == self.ST_IDLE: |
103 ptn, ptn_nbits = tms_ptns.TMS_CAP_DR | 112 ptn, ptn_nbits = tms_ptns.TMS_SHIFT_DR |
104 self._send_tms(ptn, ptn_nbits) | 113 elif self.state == self.ST_EXIT1_IR: |
105 elif self.state == self.ST_SHIFT_IR: | 114 ptn, ptn_nbits = tms_ptns.TMS_EXIT1_IR_2_SHIFT_DR |
106 ptn, ptn_nbits = tms_ptns.TMS_SHIFT_IR_2_CAP_DR | 115 elif self.state == self.ST_EXIT1_DR: |
107 self._send_tms(ptn, ptn_nbits) | 116 ptn, ptn_nbits = tms_ptns.TMS_EXIT1_DR_2_SHIFT_DR |
108 else: | 117 else: |
109 raise RuntimeError, 'Transite to shift DR state from invalid state' | 118 raise RuntimeError, 'Transite to shift DR state from invalid state' |
110 pass | 119 pass |
120 self._send_tms(ptn, ptn_nbits) | |
111 self.state = self.ST_SHIFT_DR | 121 self.state = self.ST_SHIFT_DR |
112 pass | 122 pass |
113 | 123 |
114 def shift_IR(self, data, nbits): | 124 def shift_IR(self, data, nbits): |
115 self.seq = (self.seq + 1) % 256 | 125 self.seq = (self.seq + 1) % 256 |
169 byte_off = bit_idx / 8 | 179 byte_off = bit_idx / 8 |
170 bit_off = bit_idx % 8 | 180 bit_off = bit_idx % 8 |
171 return (ord(data[byte_off]) >> bit_off) & 0x1 | 181 return (ord(data[byte_off]) >> bit_off) & 0x1 |
172 | 182 |
173 def identify_components(dev): | 183 def identify_components(dev): |
174 dev.go_shift_IR() | 184 # dev.go_shift_IR() |
175 reply = dev.wait_reply() | 185 # reply = dev.wait_reply() |
176 if reply.code != cmd_proto.CPCMD_ACK: | 186 # if reply.code != cmd_proto.CPCMD_ACK: |
177 raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) | 187 # raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) |
178 | 188 |
179 dev.shift_IR('\x02', 4) | 189 # dev.shift_IR('\x04', 4) |
180 reply = dev.wait_reply() | 190 # reply = dev.wait_reply() |
181 if reply.code != cmd_proto.CPCMD_ACK: | 191 # if reply.code != cmd_proto.CPCMD_ACK: |
182 raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) | 192 # raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) |
183 | 193 |
184 dev.go_shift_DR() | 194 dev.go_shift_DR() |
185 reply = dev.wait_reply() | 195 reply = dev.wait_reply() |
186 if reply.code != cmd_proto.CPCMD_ACK: | 196 if reply.code != cmd_proto.CPCMD_ACK: |
187 raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) | 197 raise RuntimeError, 'invalid reply code 0x%02x' % (reply.code) |