avr_jtag: src/jtag.c annotate

annotate src/jtag.c @ 13:1ea479d26fce tip

Make sure shifting phase and add bypass.py. - shifting phase is started after entering SHIFT state Transition from CAP to SHIFT does not induce shifting. - shifting phase is stoped after leaving SHIFT state. Transition from SHIFT to EXIT1 also induce a bit of shifting.

author	Thinker K.F. Li <thinker@branda.to>
date	Wed, 25 Feb 2009 20:08:29 +0800
parents	cc106f278d7d
children

rev	line source
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	1 #include <stdio.h>
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	2 #include <util/delay.h>
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	3 #include "jtag.h"
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	4 #include "avriotools.h"
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	5
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	6 /* It is supposed to work at 1Mbps */
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	7 #define CLK_DELAY() _delay_us(2)
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	8
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	9 void jtag_init(void) {
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	10 pin_mode(&JTAG_PORT, JTAG_TCK, PM_OUTPUT);
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	11 pin_mode(&JTAG_PORT, JTAG_TMS, PM_OUTPUT);
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	12 pin_mode(&JTAG_PORT, JTAG_TDI, PM_OUTPUT);
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	13 pin_mode(&JTAG_PORT, JTAG_TDO, PM_INPUT);
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	14 pin_mode(&JTAG_PORT, JTAG_TRST, PM_OUTPUT);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	15 pin_lo(JTAG_PORT, JTAG_TCK);
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	16 pin_lo(JTAG_PORT, JTAG_TMS);
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	17 pin_lo(JTAG_PORT, JTAG_TDI);
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	18 pin_hi(JTAG_PORT, JTAG_TRST);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	19 }
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	20
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	21 #define _TDI_TMS_TCK(tdi, tms, tck) \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	22 ((tms? _BV(JTAG_TMS): 0) \| \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	23 (tdi? _BV(JTAG_TDI): 0) \| \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	24 (tck? _BV(JTAG_TCK): 0))
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	25 #define _SET_PINS(pv, tdi, tms, tck) \
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	26 do { \
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	27 pv = JTAG_PORT; \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	28 pv &= ~_TDI_TMS_TCK(1, 1, 1); \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	29 pv \|= _TDI_TMS_TCK(tdi, tms, tck); \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	30 JTAG_PORT = pv; \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	31 } while(0)
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	32 #define SEND_BIT(pv, tdi, tms) \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	33 do { \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	34 _SET_PINS(pv, tdi, tms, 0); \
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	35 CLK_DELAY(); \
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	36 _SET_PINS(pv, tdi, tms, 1); \
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	37 CLK_DELAY(); \
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	38 } while(0)
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	39 #define GET_TDO() (JTAG_PIN & _BV(JTAG_TDO))
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	40 #define SEND_GET_BIT(pv, tdi, tms, out) \
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	41 do { \
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	42 _SET_PINS(pv, tdi, tms, 0); \
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	43 CLK_DELAY(); \
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	44 out = GET_TDO(); \
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	45 _SET_PINS(pv, tdi, tms, 1); \
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	46 CLK_DELAY(); \
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	47 } while(0)
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	48
7 61f27549de57 Support TRST. Thinker K.F. Li <thinker@branda.to> parents: 5 diff changeset	49 void jtag_trst(void) {
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	50 unsigned char pv;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	51
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	52 pin_lo(JTAG_PORT, JTAG_TCK);
7 61f27549de57 Support TRST. Thinker K.F. Li <thinker@branda.to> parents: 5 diff changeset	53 pin_lo(JTAG_PORT, JTAG_TRST);
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	54
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	55 SEND_BIT(pv, 1, 1);
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	56 SEND_BIT(pv, 1, 1);
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	57 SEND_BIT(pv, 1, 1);
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	58 SEND_BIT(pv, 1, 1);
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	59 SEND_BIT(pv, 1, 1);
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	60
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	61 pin_lo(JTAG_PORT, JTAG_TCK);
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	62 pin_hi(JTAG_PORT, JTAG_TRST);
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	63
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	64 SEND_BIT(pv, 1, 1);
7 61f27549de57 Support TRST. Thinker K.F. Li <thinker@branda.to> parents: 5 diff changeset	65 }
61f27549de57 Support TRST. Thinker K.F. Li <thinker@branda.to> parents: 5 diff changeset	66
5 eb14cac68cbb Transite TAP controller to shift state. Thinker K.F. Li <thinker@branda.to> parents: 4 diff changeset	67 /*!
eb14cac68cbb Transite TAP controller to shift state. Thinker K.F. Li <thinker@branda.to> parents: 4 diff changeset	68 * Before shifting registers, TAP controller must move to last state before
eb14cac68cbb Transite TAP controller to shift state. Thinker K.F. Li <thinker@branda.to> parents: 4 diff changeset	69 * shift state. The state machine transite to shift state when shifting
eb14cac68cbb Transite TAP controller to shift state. Thinker K.F. Li <thinker@branda.to> parents: 4 diff changeset	70 * starts.
eb14cac68cbb Transite TAP controller to shift state. Thinker K.F. Li <thinker@branda.to> parents: 4 diff changeset	71 */
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	72 void jtag_tms(unsigned char *buf, int nbits) {
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	73 int i;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	74 int nbytes;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	75 int byteoff, bitoff;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	76 unsigned char byte;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	77 unsigned char bit;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	78 unsigned char pv;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	79
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	80 nbytes = nbits / 8;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	81 for(i = 0; i < nbytes; i++) {
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	82 byte = buf[i];
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	83
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	84 bit = byte & 0x01;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	85 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	86
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	87 bit = byte & 0x02;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	88 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	89
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	90 bit = byte & 0x04;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	91 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	92
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	93 bit = byte & 0x08;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	94 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	95
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	96 bit = byte & 0x10;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	97 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	98
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	99 bit = byte & 0x20;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	100 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	101
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	102 bit = byte & 0x40;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	103 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	104
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	105 bit = byte & 0x80;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	106 SEND_BIT(pv, 1, bit);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	107 }
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	108
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	109 byte = buf[i];
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	110 nbits %= 8;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	111 for(i = 0; i < nbits; i++) {
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	112 bit = byte & (1 << i);
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	113 SEND_BIT(pv, 1, bit);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	114 }
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	115 }
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	116
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	117 void jtag_shift(unsigned char *buf, int nbits) {
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	118 int i;
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	119 int nbits_1;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	120 int nbytes;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	121 int remain;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	122 int byteoff, bitoff;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	123 unsigned char byte;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	124 unsigned char bit;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	125 unsigned char pv;
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	126
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	127 if(nbits == 0)
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	128 return;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	129
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	130 nbits_1 = nbits - 1;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	131 nbytes = nbits_1 / 8;
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	132 for(i = 0; i < nbytes; i++) {
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	133 byte = buf[i];
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	134
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	135 bit = byte & 0x01;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	136 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	137
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	138 bit = byte & 0x02;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	139 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	140
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	141 bit = byte & 0x04;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	142 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	143
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	144 bit = byte & 0x08;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	145 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	146
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	147 bit = byte & 0x10;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	148 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	149
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	150 bit = byte & 0x20;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	151 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	152
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	153 bit = byte & 0x40;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	154 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	155
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	156 bit = byte & 0x80;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	157 SEND_BIT(pv, bit, 0);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	158 }
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	159
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	160 remain = nbits_1 % 8;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	161 byte = buf[i];
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	162 for(i = 0; i < remain; i++) {
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	163 bit = byte & (1 << i);
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	164 SEND_BIT(pv, bit, 0);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	165 }
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	166
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	167 byte = buf[nbits / 8];
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	168 bit = byte & (1 << (nbits_1 % 8));
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	169
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	170 SEND_BIT(pv, bit, 1);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	171 }
abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	172
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	173 void jtag_shift_inout(unsigned char ibuf, unsigned char obuf, int nbits) {
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	174 int i, j;
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	175 int nbits_1;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	176 int nbytes;
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	177 int tdo;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	178 int byteoff, bitoff;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	179 int remain;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	180 unsigned char byte, obyte;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	181 unsigned char bit;
1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	182 unsigned char pv;
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	183
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	184 if(nbits == 0)
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	185 return;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	186
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	187 nbits_1 = nbits - 1;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	188 nbytes = nbits_1 / 8;
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	189 for(i = 0; i < nbytes; i++) {
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	190 byte = ibuf[i];
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	191 obyte = 0;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	192
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	193 bit = byte & 0x01;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	194 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	195 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	196 obyte \|= 0x01;
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	197
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	198 bit = byte & 0x02;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	199 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	200 tdo = GET_TDO();
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	201 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	202 obyte \|= 0x02;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	203
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	204 bit = byte & 0x04;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	205 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	206 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	207 obyte \|= 0x04;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	208
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	209 bit = byte & 0x08;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	210 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	211 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	212 obyte \|= 0x08;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	213
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	214 bit = byte & 0x10;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	215 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	216 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	217 obyte \|= 0x10;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	218
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	219 bit = byte & 0x20;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	220 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	221 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	222 obyte \|= 0x20;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	223
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	224 bit = byte & 0x40;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	225 SEND_GET_BIT(pv, bit, 0, tdo);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	226 if(tdo)
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	227 obyte \|= 0x40;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	228
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	229 bit = byte & 0x80;
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	230 SEND_GET_BIT(pv, bit, 0, tdo);
4 6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	231 if(tdo)
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	232 obyte \|= 0x80;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	233
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	234 obuf[i] = obyte;
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	235 }
6b1594fb668f Improve performance of jtag.c and test it with Python scripts. Thinker K.F. Li <thinker@branda.to> parents: 2 diff changeset	236
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	237 remain = nbits_1 % 8;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	238 byte = ibuf[i];
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	239 obyte = 0;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	240 for(j = 0; j < remain; j++) {
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	241 bit = byte & (1 << j);
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	242 SEND_GET_BIT(pv, bit, 0, tdo);
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	243 if(tdo)
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	244 obyte \|= 1 << j;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	245 else
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	246 obyte &= ~(1 << j);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	247 }
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	248 obuf[i] = obyte;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	249
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	250 byte = ibuf[nbits / 8];
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	251 bit = byte & (1 << (nbits_1 % 8));
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	252
13 1ea479d26fce Make sure shifting phase and add bypass.py. Thinker K.F. Li <thinker@branda.to> parents: 10 diff changeset	253 SEND_GET_BIT(pv, bit, 1, tdo);
10 cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	254 if(tdo)
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	255 obuf[nbits / 8] \|= 1 << j;
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	256 else
cc106f278d7d Get identify of components Thinker K.F. Li <thinker@branda.to> parents: 7 diff changeset	257 obuf[nbits / 8] &= ~(1 << j);
2 abf221bf3ce4 AVR JTAG server. Thinker K.F. Li <thinker@branda.to> parents: diff changeset	258 }

Mercurial > avr_jtag

annotate src/jtag.c @ 13:1ea479d26fce tip